Semiconductor device, imaging device, and electronic device

ABSTRACT

Provided is a novel semiconductor device, a semiconductor device with reduced area, or a versatile semiconductor device. The semiconductor device includes a pixel portion including a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first to fourth pixels; a first wiring located outside the first to fourth pixels; a second wiring electrically connected to the first and second pixels; and a third wiring electrically connected to the third and fourth pixels. A first terminal of the first switch is electrically connected to the first wiring. A second terminal of the first switch is electrically connected to the second wiring. A first terminal of the second switch is electrically connected to the first wiring. A second terminal of the second switch is electrically connected to the third wiring.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a semiconductordevice, an imaging device, and an electronic device.

One embodiment of the present invention is not limited to the abovetechnical field. The technical field of one embodiment of the inventiondisclosed in this specification and the like relates to an object, amethod, or a manufacturing method. One embodiment of the presentinvention relates to a process, a machine, manufacture, or a compositionof matter. One embodiment of the present invention relates to asemiconductor device, a display device, a lighting device, a powerstorage device, a memory device, or a driving method or manufacturingmethod thereof.

2. Description of the Related Art

A technological development of a photodetector including a photodetectorcircuit (also referred to as an optical sensor) capable of generatingdata having a value corresponding to the illuminance of incident lighthas been advanced.

An image sensor is an example of the photodetector. Examples of theimage sensor include a charge coupled device (CCD) image sensor and acomplementary metal oxide semiconductor (CMOS) image sensor. The CMOSimage sensor is generally used as an imaging element in portabledevices, such as digital cameras or cellular phones. In recent years, apixel in the CMOS image sensor has been made smaller in accordance withthe increase in definition of imaging and the reduction in size andpower consumption of portable devices.

Patent Document 1 discloses an imaging element in which a transistor isshared by adjacent pixels to reduce the pixel area.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    11-126895

SUMMARY OF THE INVENTION

If an element, such as a transistor, included in an image sensor isshared by a plurality of pixels, a certain area in a pixel region isoccupied by the element because the shared element is provided in thepixel region. Thus, there is a limit to reduction in the area of thepixel region by the element sharing among pixels in the pixel region.

In addition, an amplifier and a reset transistor are connected to thesame power source line in Patent Document 1. Because of this, powervoltage for the amplifier and power voltage for the reset transistorcannot be determined separately, and the degree of freedom of pixeldesign is decreased. However, in the case where different power sourcelines are provided for the amplifier and the reset transistor, space fortwo power source lines needs to be provided in a pixel, which leads toincrease in the pixel area and reduction in the aperture ratio.

An object of one embodiment of the present invention is to provide anovel semiconductor device. Another object of one embodiment of thepresent invention is to provide a semiconductor device with reducedarea. Another object of one embodiment of the present invention is toprovide a versatile semiconductor device. Another object of oneembodiment of the present invention is to provide a semiconductor devicecapable of high-resolution imaging. Another object of one embodiment ofthe present invention is to provide a semiconductor device capable ofreducing power consumption. Another object of one embodiment of thepresent invention is to provide a semiconductor device capable ofhigh-speed imaging.

One embodiment of the present invention does not necessarily achieve allthe objects listed above and only needs to achieve at least one of theobjects. The description of the above objects does not disturb theexistence of other objects. Other objects are apparent from and can bederived from the description of the specification, the drawings, and theclaims.

Means for Solving the Problems

A semiconductor device according to one embodiment of the presentinvention includes a pixel portion including a first pixel, a secondpixel, a third pixel, and a fourth pixel; a first switch and a secondswitch located outside the first pixel, the second pixel, the thirdpixel, and the fourth pixel; a first wiring located outside the firstpixel, the second pixel, the third pixel, and the fourth pixel; a secondwiring electrically connected to the first pixel and the second pixeland a third wiring electrically connected to the third pixel and thefourth pixel. A first terminal of the first switch is electricallyconnected to the first wiring. A second terminal of the first switch iselectrically connected to the second wiring. A first terminal of thesecond switch is electrically connected to the first wiring. A secondterminal of the second switch is electrically connected to the thirdwiring.

A semiconductor device according to one embodiment of the presentinvention includes a pixel portion including a first pixel, a secondpixel, a third pixel, and a fourth pixel; a first switch and a secondswitch located outside the first pixel, the second pixel, the thirdpixel, and the fourth pixel; a first wiring located outside the firstpixel, the second pixel, the third pixel, and the fourth pixel; a secondwiring electrically connected to the first pixel and the second pixel;and a third wiring electrically connected to the third pixel and thefourth pixel. A first terminal of the first switch is electricallyconnected to the first wiring. A second terminal of the first switch iselectrically connected to the second wiring. A first terminal of thesecond switch is electrically connected to the first wiring. A secondterminal of the second switch is electrically connected to the thirdwiring. The semiconductor device according to one embodiment of thepresent invention includes a first step for resetting the first pixel,the second pixel, the third pixel, and the fourth pixel; a second stepfor turning the first switch on, supplying a potential of the firstwiring to the second wiring, and reading an electric signal from thefirst pixel and the second pixel after the first step; a third step forresetting the first pixel, the second pixel, the third pixel, and thefourth pixel after the second step; and a fourth step for turning thesecond switch on, supplying a potential of the first wiring to the thirdwiring, and reading an electric signal from the third pixel and thefourth pixel after the third step.

The semiconductor device according to one embodiment of the presentinvention may further include a fourth wiring capable of supplying areset potential to the first pixel, the second pixel, the third pixel,and the fourth pixel. A potential higher than the fourth wiring may besupplied to the first wiring.

In the semiconductor device according to one embodiment of the presentinvention, each of the first pixel, the second pixel, the third pixel,and the fourth pixel may include a photoelectric conversion element anda transistor. The photoelectric conversion element may be electricallyconnected to the transistor. A channel formation region of thetransistor may include an oxide semiconductor.

In the semiconductor device according to one embodiment of the presentinvention, the first switch and the second switch may include a firsttransistor and a second transistor, respectively. Each of the firstpixel, the second pixel, the third pixel, and the fourth pixel mayinclude a photoelectric conversion element and a third transistor. Thephotoelectric conversion element may be electrically connected to thethird transistor. A channel formation region of each of the firsttransistor and the second transistor may include a single-crystalsemiconductor. A channel formation region of the third transistor mayinclude an oxide semiconductor. The third transistor may be stacked overthe first transistor and the second transistor.

In the semiconductor device according to one embodiment of the presentinvention, the photoelectric conversion element may include a firstelectrode, a second electrode, and a photoelectric conversion layerbetween the first electrode and the second electrode. The photoelectricconversion layer may contain selenium.

An imaging device of one embodiment of the present invention includes aphotodetector portion including the semiconductor device, and a dataprocessing portion having a function of generating an image data on thebasis of a signal from the photodetector portion.

An electronic device of one embodiment of the present invention includesone of the semiconductor device and the imaging device and at least oneof a lens, a display portion, an operation key, and a shutter button.

According to one embodiment of the present invention, a novelsemiconductor device, a semiconductor device with reduced area, aversatile semiconductor device, a semiconductor device capable ofhigh-resolution imaging, a semiconductor device capable of reducingpower consumption, or a semiconductor device capable of high-speedimaging.

Note that the description of these effects does not disturb theexistence of other effects. One embodiment of the present invention doesnot necessarily achieve all the effects listed above. Other effects willbe apparent from and can be derived from the description of thespecification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a structure example of a semiconductordevice.

FIG. 2 is a circuit diagram illustrating a structure example of asemiconductor device.

FIG. 3 is a circuit diagram illustrating a structure example of asemiconductor device.

FIG. 4 is a timing chart.

FIG. 5 is a diagram illustrating a structure example of a pixel.

FIGS. 6A, 6B, 6C, and 6D are circuit diagrams each illustrating astructure example of a pixel.

FIGS. 7A and 7B are circuit diagrams each illustrating a structureexample of a pixel.

FIGS. 8A, 8B, 8C, and 8D are circuit diagrams each illustrating astructure example of a pixel.

FIG. 9 is a circuit diagram illustrating a structure example of a pixelportion.

FIG. 10 is a diagram illustrating a structure example of an imagingdevice.

FIGS. 11A, 11B, and 11C are diagrams each illustrating a cross-sectionalstructure example of a semiconductor device.

FIGS. 12A, 12B, and 12C are diagrams each illustrating a cross-sectionalstructure example of a semiconductor device.

FIGS. 13A and 13B are diagrams each illustrating a cross-sectionalstructure example of a semiconductor device.

FIGS. 14A and 14B are diagrams each illustrating a structure example ofan imaging device.

FIGS. 15A, 15B, and 15C are diagrams each illustrating a structureexample of a pixel.

FIGS. 16A and 16B are diagrams illustrating a structure example of atransistor.

FIGS. 17A1, 17A2, 17B1, and 17B2 are diagrams each illustrating astructure example of a transistor.

FIGS. 18A1, 18A2, 18A3, 18B1, and 18B2 are diagrams each illustrating astructure example of a transistor.

FIGS. 19A, 19B, and 19C are diagrams illustrating a structure example ofa transistor.

FIGS. 20A, 20B, and 20C are diagrams illustrating a structure example ofa transistor.

FIGS. 21A, 21B, and 21C are diagrams illustrating a structure example ofa transistor.

FIGS. 22A, 22B, 22C, 22D, 22E, and 22F are diagrams each illustrating anelectronic device.

DETAILED DESCRIPTION OF THE INVENTION Best Mode for Carrying Out theInvention

Hereinafter, embodiments of the present invention will be describedbelow in detail with reference to the accompanying drawings. Note thatthe present invention is not limited to the following description and itis easily understood by those skilled in the art that the mode anddetails can be variously changed without departing from the scope andspirit of the present invention. Therefore, the present invention shouldnot be interpreted as being limited to the embodiments.

One embodiment of the present invention includes, in its category,devices such as an imaging device, a radio frequency (RF) tag, a displaydevice, and an integrated circuit. The display device includes, in itscategory, a display device including an integrated circuit, such as aliquid crystal display device, a light-emitting device in which alight-emitting element typified by an organic light-emitting element isprovided in each pixel, an electronic paper, a digital micromirrordevice (DMD), a plasma display panel (PDP), and a field emission display(FED).

The same reference numerals are sometimes used for the same element indifferent drawings of the present invention.

In this specification and the like, the explicit description of X and Yare connected means that X and Y are connected to each otherelectrically, functionally, or directly. Accordingly, without beinglimited to a connection relationship shown in drawings orspecifications, another connection relationship is included therein.Here, X and Y denote an object (e.g., a device, an element, a circuit, awiring or line, an electrode, a terminal, a conductive film, and alayer).

In the condition that X and Y are directly connected to each other, forexample, X and Y are connected without an element capable ofelectrically connecting X and Y (e.g., a switch, a transistor, acapacitor, an inductor, a resistor, a diode, a display element, alight-emitting element, and a load) provided therebetween.

In the condition that X and Y are electrically connected to each other,one or more elements capable of electrically connecting X and Y (e.g., aswitch, a transistor, a capacitor, an inductor, a resistor, a diode, adisplay element, a light-emitting element, or a load) can be connectedbetween X and Y. A switch is turned on and off and controlled. That is,a switch has a function of controlling the flow of current when turnedon and off. Alternatively, the switch has a function of selecting andchanging a current path. Note that the description of X and Y areelectrically connected includes X and Y are directly connected.

In the condition that X and Y are functionally connected, one or morecircuits capable of functionally connecting X and Y (e.g., a logiccircuit such as an inverter, a NAND circuit, or a NOR circuit; a signalconverter circuit such as a DA converter circuit, an AD convertercircuit, or a gamma correction circuit; a potential level convertercircuit such as a power supply circuit (e.g., a step-up circuit or astep-down circuit) or a level shifter circuit for changing the potentiallevel of a signal; a voltage source; a current source; a switchingcircuit; an amplifier circuit such as a circuit that can increase signalamplitude, the amount of current, or the like, an operational amplifier,a differential amplifier circuit, a source follower circuit, or a buffercircuit; a signal generation circuit; a memory circuit; and/or a controlcircuit) can be connected between X and Y. For example, the case where asignal output from X is transmitted to Y even when another circuit isprovided between X and Y is also included. Note that the case where Xand Y are functionally connected includes the case where X and Y aredirectly connected and the case where X and Y are electricallyconnected.

In this specification and the like, the explicit description of X and Yare electrically connected means that X and Y are electrically connected(i.e., X and Y are connected with another element or another circuitprovided therebetween), X and Y are functionally connected (i.e., thecase where X and Y are functionally connected with another circuitprovided therebetween), and X and Y are directly connected (i.e., thecase where X and Y are connected without another element or anothercircuit provided therebetween). That is, in this specification and thelike, the explicit description of X and Y are electrically connected isthe same as X and Y are connected.

One component actually has functions of a plurality of components insome cases, though independent components are electrically connected toeach other in a diagram. For example, when part of a wiring has afunction of an electrode, a conductive film forming the wiring has afunction of not only the wiring but also the electrode. Thus,“electrical connection” in this specification includes in its categorysuch a case where a conductive film has functions of a plurality ofcomponents.

Embodiment 1

In this embodiment, a structure example of a semiconductor device of oneembodiment of the present invention is described.

<Structure Example of Semiconductor Device 10>

FIG. 1 illustrates a structure example of a semiconductor device 10 ofone embodiment of the present invention. The semiconductor device 10includes a pixel portion 20, a circuit 30, and a circuit 40. Thesemiconductor device 10 further includes a wiring VIN and a plurality ofswitches S outside the pixel portion 20.

The pixel portion 20 includes a plurality of pixels 21. Shown here is anexample in which the pixels 21[1,1] to 21[n,m] are provided in n rowsand m columns (n and m are natural numbers) in the pixel portion 20.Each pixel 21 has a function of converting irradiation light into anelectrical signal (hereinafter also referred to as an optical datasignal). Each pixel 21 thus serves as a photodetector circuit in animaging device. Specifically, irradiation light of a photoelectricconversion element provided in each pixel 21 is converted into anelectrical signal.

Each pixel 21 is connected to a wiring SE and a wiring OUT.Specifically, pixels 21 in the i-th row (i is an integer greater than orequal to 1 and less than or equal to n), i.e., a pixel 21[i,1] to apixel 21[i,m] are connected to a wiring SEW; and pixels 21 in the j-throw (j is an integer greater than or equal to 1 and less than or equalto m), i.e., a pixel 21[1,j] to a pixel 21[n,j] are connected to awiring OUT[j]. An optical data signal generated in each pixel 21 isoutput to the circuit 40 through the wiring OUT.

Note that a pixel 21 receiving red light, a pixel 21 receiving greenlight, and a pixel 21 receiving blue light each of which generates anoptical data signal may be provided in the circuit 20. The optical datasignals are synthesized with each other to generate a data signal of afull-color image signal. Instead of or in addition to these pixels 21, apixel 21 receiving light exhibiting one or more of cyan, magenta, andyellow may be provided, in which case the number of reproducible colorsin an image, which is displayed based on image signals generated by thepixels 21, can be increased. For example, by providing a coloring layer,which transmits light of a particular color, in a pixel 21 and lettinglight enter the pixel 21 through the coloring layer, the optical datasignal in accordance with the amount of light of a particular color canbe generated. Light detected in the pixel 21 can be visible orinvisible.

The pixel 21 may be provided with a cooling unit, which suppressesoccurrence of noise due to heat.

The circuit 30 is a driver circuit having a function of selecting pixels21 in a specific row from the pixels 21 in n rows. The circuit 30selects the pixels 21 in a specific row outputting optical data signals.Specifically, the circuit 30 outputs a control signal to a plurality ofswitches S (switches S1 to Sn) to control conductions of the pluralityof switches S so that pixels 21 in a specific row can be selected. Thecircuit 30 can include a decoder, for example.

Note that the circuit 30 may have a function of supplying a reset signalto the pixels 21.

The circuit 40 is a read circuit having a function of outputting theoptical data signal, which is obtained in the pixel portion, to theoutside. Specifically, the circuit 40 is connected to the pixels 21through the wirings OUT and has a function of outputting the opticaldata signal, which is input from predetermined pixels 21 through thewiring OUT, to the outside. The circuit 40 can include a current source,a transistor, and the like.

In addition, the circuit 40 has a function of supplying a predeterminedpotential to the wiring OUT, and accordingly the potential of the wiringOUT which is used for outputting the signal generated in the pixels 21to the outside can be reset. The circuit 40 can also serve as a constantcurrent source, which enables supply of a predetermined potential to thewiring OUT in accordance with the signal, which is input from the pixels21.

In addition, the semiconductor device 10 includes the plurality ofswitches S (the switches S1 to Sn) and a wiring VIN outside the pixelportion 20. A first terminal and a second terminal of a switch Si areconnected to the wiring SE[i] and the wiring VIN, respectively. Theswitches S each have a function of controlling electrical connectionbetween the wirings SE and VIN in accordance with the control signalinput from the circuit 30.

The wiring VIN is a power source line used for outputting an opticaldata signal. When the switch Si is turned on and the wiring VIN iselectrically connected to the wiring SE[i], an optical data signal isoutput from the pixels 21[i,1] to 21[i,m], which are connected to thewiring SE[i], to the circuit 40.

For example, in order to read an optical data signal from the pixels21[1,1] to 21[1,m] in the first row, a predetermined control signal isoutput from the circuit 40 to the switch S1 to turn the switch S1 on.Accordingly, the wiring SE[1] is electrically connected to the wiringVIN, and the potential (power source potential) of the power source lineVIN is supplied to the pixels 21[1,1] to 21[1,m], so that the opticaldata signal can be read out.

As described, in one embodiment of the present invention, the switches Sfor selecting the pixels 21 are shared by the pixels 21 in one row andare provided outside the pixel portion 20. Thus, a switch (e.g., atransistor) for selecting the pixels 21 and a power source lineconnected to the switch need not be provided in the pixel portion 20,which leads to the reduction in the area of the pixel portion 20.

In addition, in one embodiment of the present invention, the wiring VINfunctioning as a power source line for reading an optical data signalfrom the pixels 21 is provided outside the pixel portion 20. Thus, ifthe wiring VIN is formed using a wiring different from a wiring (e.g., areset power source line) connected to the pixels 21, the area of thepixel portion 20 is not increased. Since a potential different from thatsupplied to the power source line connected to the pixels 21 can be thussupplied to the wiring VIN, a power potential used for reading anoptical data signal can be freely determined, which leads to animprovement of the freedom degree of design and the versatility of thesemiconductor device 10.

Note that it is preferable that the wiring SE be not electricallyconnected to the wiring OUT in rows other than the row where an opticaldata signal is read, in which case the optical data signal can be readmore accurately.

<Another Example of Circuit Configuration>

Next, a specific circuit configuration of the semiconductor device 10 isdescribed. FIG. 2 shows an example of a circuit configuration of thesemiconductor device 10 including the pixel 21 and a circuit 41.Although all of the transistors are n-channel transistors in thenon-limiting example, each of the transistors described below may be ann-channel transistor or a p-channel transistor.

First, a structure example of the pixel 21 is described.

The pixel 21 shown in FIG. 2 includes a photoelectric conversion element101, transistors 102, 103, and 104, and a capacitor 105. A firstterminal and a second terminal of the photoelectric conversion element101 are connected to one of a source and drain of the transistor 102 anda wiring VPD, respectively. A gate and the other of the source and drainof the transistor 102 are connected to a wiring TX and a gate of thetransistor 104, respectively. A gate of the transistor 103 is connectedto a wiring PR, one of a source and drain of the transistor 104 isconnected to the gate of the transistor 104, and the other of the sourceand drain of the transistor 104 is connected to a wiring VPR. One of thesource and drain of the transistor 104 and the other thereof areconnected to the wiring SE and the wiring OUT, respectively. One ofelectrodes of the capacitor 105 and the other thereof are connected tothe gate of the transistor 104 and the wiring VPD, respectively. A nodeconnected to the other of the source and drain of the transistor 102,the one of the source and drain of the transistor 103, the gate of thetransistor 104, and the one of electrodes of the capacitor 105 isreferred to as a node FN. Note that the capacitor 105 can be formedusing a capacitor element or a parasitic capacitance. If the gatecapacitance of the transistor 104 is sufficiently large, the capacitor105 and the wiring VPD can be omitted.

Note that a “source” of a transistor in this specification means asource region that is part of a semiconductor functioning as an activelayer or a source electrode connected to the semiconductor. Similarly, a“drain” of the transistor means a drain region that is part of thesemiconductor or a drain electrode connected to the semiconductor. A“gate” means a gate electrode.

The terms “source” and “drain” of a transistor interchange with eachother depending on the conductivity type of the transistor or levels ofpotentials applied to the terminals. In general, in an n-channeltransistor, a terminal to which a lower potential is applied is called asource, and a terminal to which a higher potential is applied is calleda drain. In a p-channel transistor, a terminal to which a lowerpotential is applied is called a drain, and a terminal to which a higherpotential is applied is called a source. In this specification, althoughconnection relation of the transistor is described assuming that thesource and the drain are fixed in some cases for convenience, actually,the names of the source and the drain interchange with each otherdepending on the relation of the potentials.

Each of the wirings VPD and VPR is supplied with a predeterminedpotential and functions as a power source line. A potential supplied toeach of the wirings VPD and VPR may be a high power source potential ora low power source potential (e.g., a ground potential). Described hereis the case where the wirings VPD and VPR are a high potential powersource line and a low potential power source line, respectively. Thatis, a high power source potential VDD is supplied to the wiring VPD,whereas a low power source potential VSS is supplied to the wiring VPR.The wirings VPD and VPR may be shared by all the pixels 21.

The photoelectric conversion element 101 has a function of convertingirradiation light into an electrical signal. An element with whichphotocurrent can be obtained in accordance with the amount ofirradiation light can be used as the photoelectric conversion element101. A PN photodiode, a PIN photodiode, an avalanche diode, an NPNburied diode, a Schottky diode, a phototransistor, an X-rayphotoconductor, an infrared ray sensor, and the like can be given asspecific examples of the photoelectric conversion element 101. Inaddition, an element containing selenium in a photoelectric conversionlayer can be used as the photoelectric conversion element 101. In FIG.2, a photodiode is used as the photoelectric conversion element 101. Ananode and a cathode of the photodiode are connected to one of the sourceand drain of the transistor 102 and the wiring VPD, respectively. Notethat in the case where the low power source potential VSS and the highpower source potential VDD are supplied to the wirings VPD and VPR,respectively, the anode and cathode of the photodiode are preferablyinterchanged.

The on/off state of the transistor 102 is controlled by a potential ofthe wiring TX. If the transistor 102 is on, an electrical signal outputfrom the photoelectric conversion element 101 is supplied to the nodeFN. Thus, the potential of the node FN is determined by the amount ofirradiation light on the photoelectric conversion element 101. Lightexposure can be performed in a period during which the transistors 102and 103 are on and off, respectively.

The on/off state of the transistor 103 is controlled by the potential ofthe wiring PR. When the transistor 103 is turned on, the potential ofthe wiring VPR is supplied to the node FN to reset the potential of thenode FN. The potential of the wiring PR at which the transistor 103 isturned on corresponds to a reset signal, and a period during which thereset signal is supplied to the wiring PR corresponds to a reset period.Note that the potential of the wiring PR may be controlled by thecircuit 30 or another driver circuit.

In order to reset the pixel 21, the potential of the wiring VPR issupplied to the node FN as described above. Such a potential of thewiring VPR for resetting the pixel 21 is also referred to as a resetpotential.

The on/off state of the transistor 104 is controlled by the potential ofthe node FN. Specifically, the source-drain resistance value of thetransistor 104 changes in accordance with the potential of the node FN.A potential to be supplied from the wiring SE to the wiring OUT via thetransistor 104 is determined by the potential of the node FN.

In one embodiment of the present invention, the potential of the wiringSE is controlled by the transistor 110 and the wiring VIN. A gate of thetransistor 110 is connected to a wiring CSE, one of a source and drainthereof is connected to the wiring SE, and the other of the source anddrain thereof is connected to the wiring VIN. Note that the transistor110 corresponds to the switch S in FIG. 1. When a potential at which thetransistor 110 is turned on (hereinafter such a potential is alsoreferred to as a selection signal) is supplied to the wiring CSE, thewiring VIN is electrically connected to the wiring SE, and the potentialof the wiring VIN is supplied to the pixel 21 as a power sourcepotential. The pixel 21 from which an optical data signal is read canthus be selected.

The transistor 110 for selecting from among the pixels 21 is shared bypixels 21 in one row and is provided outside the pixels 21; thus, thenumber of transistors included in each pixel 21 and the area of eachpixel 21 can be reduced.

Next, a configuration of the circuit 41 is described.

The circuit 41 is included in the circuit 40 shown in FIG. 1. Describedhere is a structure example in which the circuit 41 is provided for eachrow of pixels 21.

The circuit 41 includes a transistor 120. A gate of the transistor 120is connected to a wiring BR, one of a source and drain of the transistor120 is connected to a wiring VO, and the other of the source and drainof the transistor 120 is connected to the wiring OUT.

The on/off state of the transistor 120 is controlled in accordance witha potential of the wiring BR. When the transistor 120 is turned on, thepotential of the wiring VO is supplied to the wiring OUT to reset thepotential of the wiring OUT. Then, when a power source potential issupplied to the wiring SE from the wiring VIN through the transistor110, the potential corresponding to the node FN is output to the wiringOUT. The transistor 104 is used in a source follower, and the potentialof the node FN lowered by the threshold voltage of the transistor 104 isoutput to the wiring OUT.

The wiring VO is supplied with a predetermined potential and serves as apower source line. A potential supplied to the wiring VO may be a highpower source potential or a low power source potential (e.g., a groundpotential). Described here is the case where the wiring VO is a lowpotential power supply line. That is, the low power supply potential VSSis supplied to the wiring VO.

Note that while a predetermined potential at which the transistor 120 ison is continuously supplied to the wiring BR, the transistor 120 servesas a current source. A potential obtained by resistance division ofcombined resistance of the source-drain resistance of the transistor 120and the source-drain resistance of the transistor 104 is output to thewiring OUT.

In one embodiment of the present invention, the wiring VIN is separatedfrom the wiring VPR, and a potential different from a potential suppliedto the wiring VPR can be supplied to the wiring VIN. For example, whenthe low power source potential VSS is supplied to the wiring VPR, thehigh power source potential VDD can be supplied to the wiring VIN. Thus,a source follower can be formed with the transistors 104 and 120 to readan optical data signal at high speed. The dynamic range of the outputpotential of the wiring OUT can be changed by adjustments of the highpower source potential VDD supplied to the wiring VIN.

<Example of Reading Operation>

Next, operation for reading an optical data signal from the pixel 21will be described.

In order to read an optical data signal from the pixel 21 in FIG. 2, thepotential of the signal line CSE is set high to turn the transistor 110on, and the high power source potential VDD is accordingly supplied fromthe wiring VIN to the wiring SE. In this state, the source-drainresistance value of the transistor 104 corresponds to the node FN, andthe potential corresponding to the potential of the node FN is outputfrom the wiring SE through the transistor 104 to the wiring OUT;accordingly, an optical data signal can be read from the pixel 21.

In a period during which an optical data signal is not read from thepixel 21, the potential of the signal line CSE is set low to turn thetransistor 110 off. The power source potential is not supplied from thewiring VIN to the wiring SE in this state, and thus an optical datasignal is not output to the wiring OUT.

In the period during which an optical data signal is not read, it ispreferable that the pixel 21 be reset; specifically, it is preferablethat the node FN be low and the transistor 104 be off, wherebyelectrical connection between the wirings SE and OUT can be cut toprevent supply of an undesired potential to the wiring OUT. In order toturn the transistor 104 off, the transistor 103 is turned on to supplythe low power source potential VSS of the wiring VPR to the node FN.

The above-described operation can output an optical data signal to thewiring OUT. The optical data signal output to the wiring OUT is input tothe circuit 40 and output to the outside from the circuit 40.

Although there is no particular limitation on materials and the likeused for the transistors shown in FIG. 2, it is particularly preferableto use a transistor in which an oxide semiconductor is used in a channelformation region (hereinafter also referred to as an OS transistor) forthe transistors 102, 103, and 104, which are included in the pixel 21.An oxide semiconductor has a wider band gap and lower intrinsic carrierdensity than other semiconductors such as silicon; therefore, theoff-state current of an OS transistor is extremely low. Thus, the use ofan OS transistor for the pixel 21 allows a predetermined potential to beheld for a long time. The details of an oxide semiconductor and an OStransistor will be described in Embodiments 4 and 7.

When an OS transistor is used as the transistor 102, for example, chargetransfer between the node FN and the photoelectric conversion element101 can be suppressed while the transistor 102 is off; accordingly,charge accumulated in the node FN can be held for an extremely long timeto prevent a potential change of the node FN.

When an OS transistor is used as the transistor 103, charge transferbetween the node FN and the wiring VPR can be suppressed while thetransistor 103 is off; accordingly, charge accumulated in the node FNcan be held for an extremely long time to prevent a potential change ofthe node FN.

When an OS transistor is used as the transistor 104, for example, chargetransfer between the wirings SE and OUT can be suppressed while thetransistor 104 is off; accordingly, an undesired potential change of thewiring OUT can be suppressed. Thus, when a transistor 104 in one pixel21 is off, an optical data signal in the other pixel 21 connected to thesame wiring OUT can be read more accurately.

In addition, the use of OS transistors as the transistors 102 and 103allows the potential of the node FN to be kept stably and an opticaldata signal to be output accurately even if the potential of the node FNis extremely low. Thus, it is possible to broaden the detection range oflight illuminance, i.e., the dynamic range, of the pixel 21.

In addition, temperature dependence of variation in electricalcharacteristics is smaller in an OS transistor than a transistorcontaining silicon in a channel formation region (hereinafter, alsoreferred to as Si transistor), and thus an OS transistor can be used atan extremely wide range of temperatures. The use of a semiconductordevice including an OS transistor can provide an imaging device suitablefor use in automobiles, aircrafts, and spacecrafts.

In the case where a photoelectric conversion element in which aphotoelectric conversion layer is formed using a selenium-based materialis used as the photoelectric conversion element 101, relatively highvoltage (e.g., 10 V or higher) is preferably applied to easily cause theavalanche phenomenon. For example, the potential of the wiring VPD ispreferably higher than or equal to 10 V, and the potential of the wiringVPR is preferably 0 V. An OS transistor has higher drain breakdownvoltage than a Si transistor and thus is preferable as the transistors102 to 104. The combination of an OS transistor with a photoelectricconversion element using a selenium-based material can provide a highlyreliable imaging device capable of taking high-resolution images. Notethat the details of the photoelectric conversion element in which aphotoelectric conversion layer is formed using a selenium-based materialwill be described in Embodiment 6.

Note that the transistors 102, 103, and 104 are not limited to an OStransistor. For example, a transistor in which a channel formationregion is formed in part of a substrate including a single crystalsemiconductor to include the single crystal semiconductor in the channelformation region (hereinafter, also referred to as a single crystaltransistor) can be used. As the substrate including a single crystalsemiconductor, a single crystal silicon substrate, a single crystalgermanium substrate, or the like can be used. Since a single crystaltransistor has a high current supply ability, the operation speed of thepixel 21 using such a transistor can be increased.

Other than an OS transistor, a transistor including a non-single-crystalsemiconductor in a channel formation region (hereinafter, also referredto as a non-single-crystal transistor) can be used as the transistors102, 103, and 104. As the non-single-crystal semiconductor other than anOS transistor, non-single-crystal silicon such as amorphous silicon,microcrystalline silicon or polycrystalline silicon, non-single-crystalgermanium such as amorphous germanium, microcrystalline germanium orpolycrystalline germanium, or the like can be used.

The above-described OS transistors, single-crystal transistors, andnon-single-crystal transistors can be appropriately used as thetransistors 110 and 120.

The transistor 110 needs high current supply ability because it isconnected to a plurality of pixels 21 (m pixels 21 in FIG. 1). It isthus preferable to use a single-crystal transistor having high currentsupply ability as the transistor 110, which makes it easier to supply apower source potential from the wiring VIN to a plurality of pixels 21.In this case, the transistors 102 to 104 are preferably stacked over thetransistor 110 to suppress the increase in area caused by the transistor110. The details of the stacked structure of the transistors will bedescribed in Embodiment 4.

In the case where the transistor 110 is a transistor containing the samesemiconductor material as the transistors 102 to 104 (e.g., in the casewhere an OS transistor is used as the transistor 110 as well), thechannel width of the transistor 110 is preferably larger than that ofthe transistors 102 to 104. This can increase the current supply abilityof the transistor 110.

<Operation Example of Semiconductor Device 10>

Next, operation example of the semiconductor device 10 will be describedin detail.

Described here is an operation example of the pixels 21[1,1] and 21[1,2]in the first row and the pixels 21[2,1] and 21[2,2] in the second rowshown in FIG. 3. In FIG. 3, a wiring TX[1] and a wiring TX[2]respectively denote the wiring TX connected to the pixels 21[1,1] and21[1,2] and the wiring TX connected to the pixels 21[2,1] and 21[2,2]. Atransistor 110[1] and a transistor 110[2] respectively denote thetransistor 110 connected to the wiring SE[1] and the transistor 110connected to the wiring SE[2]. A wiring CSE[1] and a wiring CSE[2]respectively denote the wiring CSE connected to the transistor 110[1]and the wiring CSE connected to the transistor 110[2]. In addition, anode FN[1,1], a node FN[1,2], a node FN[2,1], and a node FN[2,2]respectively denote the nodes FN included in the pixels 21[1,1],21[1,2], 21[2,1], and 21[2,2]. In addition, a circuit 41[1] and acircuit 41[2] respectively denote the circuit 41 connected to the wiringOUT[1] and the circuit 41 connected to the wiring OUT[2].

FIG. 4 is a timing chart of the semiconductor device 10 shown in FIG. 3.Note that a period Ta and a period Tb in FIG. 4 are periods for reset,light exposure, and reading in the first-row pixels and the second-rowpixels, respectively.

First, in a period T1, the potential of the wiring PR is set high, andthe transistors 103 are turned on in all the pixels 21 and the potentialof the wiring VPR (low potential) is supplied to the node FN;accordingly, the potentials of the nodes FN[1,1], FN[1,2], FN[2,1], andFN[2,2] are reset to low. The transistors 104 are turned off in all thepixels 21. The pixels 21[1,1], 21[1,2], 21[2,1], and 21[2,2] are resetby the operation.

In addition, in the pixel T1, the potential of the wiring TX[1] is sethigh to turn on the transistors 102 of the pixels 21[1,1] and 21[1,2],so that the photoelectric conversion element 101 is electricallyconnected to the node FN.

Next, in a period T2, the potential of the wiring PR is set low to turnoff the transistors 103 of all the pixels 21, and the node FN is in afloating state. Then, the potentials of the nodes FN[1,1] and FN[1,2]increase in accordance with the amount of irradiation light of thephotoelectric conversion element 101. In this example, an increase inthe potential of the node FN[1,1] is larger than that of the nodeFN[1,2]. By the operation, irradiation light of the photoelectricconversion element 101 is converted into an electrical signal and lightexposure in the pixels 21[1,1] and 21[1,2] is performed; accordingly,the period T2 is also referred to as a period for light exposure in thepixels 21[1,1] and 21[1,2].

Next, in a period T3, the potential of the wiring TX[1] is set low toturn off the transistors 102 of the pixels 21[1,1] and 21[1,2]; thus,the potentials of the node FN[1,1] and the node FN[2,2] are held and theperiod for light exposure in the pixels 21 [1,1] and 21[1,2] ends.

Then, in a period T4, the potential of the wiring BR is set high to turnthe transistor 120 on, and the potential of the wiring VO is supplied tothe wiring OUT[1] and the wiring OUT[2]. The potential of the wiring VOis low in this example, and accordingly the potentials of the wiringOUT[1] and the wiring OUT[2] are low.

Then, in a period T5, the potential of the wiring BR is set low to turnthe transistor 120 off. In addition, the potential of the wiring CSE[1]is set high to turn the transistor 110[1] on. The potential of thewiring VIN is thus supplied to the wiring SE[1], and the potential ofthe wiring SE[1] becomes high.

Although the potential of the wiring OUT is controlled by changing thepotential of the wiring BR in this example, a predetermined potentialmay be continuously supplied to wiring BR. In that case, the transistor120 serves as a current source and the potential of the wiring OUT isdetermined in accordance with the potential of the wiring BR.

In this example, the wiring SE[1] serves as a power source line for thepixels 21[1,1] and 21[1,2]. Specifically, the potential of the wiringSE[1] is supplied to the transistor 104 serving as an amplifiertransistor. Accordingly, the potentials of the wirings OUT[1] and OUT[2]become potentials corresponding to the potentials of the nodes FN[1,1]and FN[1,2], respectively. The potentials of the wirings OUT[1] andOUT[2] correspond to optical data signals of the pixels 21[1,1] and21[1,2], respectively. The transistor 110[1] in the period T5 serves asa selection transistor for selecting the pixels 21 from which an opticaldata signal is read.

In addition, the pixels 21[2,1] and 21[2,2] are reset in the period T5.Specifically, the nodes FN[2,1] and FN[2,2] are low and the transistors104 of the pixels 21 [2,1] and 21 [2,2] are off accordingly, the wiringSE[2] is not electrically connected to the wirings OUT[1] and OUT[2].This can suppress potential changes of the wirings OUT[1] and OUT[2]caused by the potential of the wiring SE[2] when optical data signalsare read from the pixels 21[1,1] and 21[1,2].

Next, in a period T6, the potential of the wiring CSE[1] is set low toturn the transistor 110[1] off. The supply of power source potential tothe wiring SE[1] is accordingly stopped, and the reading of optical datasignals ends.

Through the operation, reset, light exposure and reading are performedin the first-row pixels.

Next, in a period T7, the potential of the wiring PR is set high, andthe transistors 103 are turned on in all the pixels 21 and the potentialof the wiring VPR (low potential) is supplied to the node FN;accordingly, the potentials of the nodes FN[1,1], FN[1,2], FN[2,1], andFN[2,2] are reset to low. The transistors 104 are turned off in all thepixels 21. The pixels 21[1,1], 21[1,2], 21[2,1], and 21[2,2] are resetby the operation.

In addition, in the pixel T7, the potential of the wiring TX[2] is sethigh to turn on the transistors 102 of the pixels 21 [2,1] and 21 [2,2],so that the photoelectric conversion element 101 is electricallyconnected to the node FN.

Next, in a period T8, the potential of the wiring PR is set low to turnoff the transistors 103 of all the pixels 21, and the node FN is in afloating state. Then, the potentials of the nodes FN[2,1] and FN[2,2]increase in accordance with the amount of irradiation light of thephotoelectric conversion element 101. In this example, an increase inthe potential of the node FN[2,1] is smaller than that of the nodeFN[2,2]. By the operation, irradiation light of the photoelectricconversion element 101 is converted into an electrical signal and lightexposure in the pixels 21[2,1] and 21[2,2] is performed; accordingly,the period T8 is also referred to as a period for light exposure in thepixels 21[2,1] and 21[2,2].

Next, in a period T9, the potential of the wiring TX[2] is set low toturn off the transistors 102 of the pixels 21[2,1] and 21 [2,2]; thus,the potentials of the node FN[2,1] and the node FN[2,2] are held and theperiod for light exposure in the pixels 21 [2,1] and 21[2,2] ends.

Then, in a period T10, the potential of the wiring BR is set high toturn the transistor 120 on, and the potential of the wiring VO issupplied to the wiring OUT[1] and the wiring OUT[2]. The potential ofthe wiring VO is low in this example, and accordingly the potentials ofthe wiring OUT[1] and the wiring OUT[2] are low.

Then, in a period T11, the potential of the wiring BR is set low to turnthe transistor 120 off. In addition, the potential of the wiring CSE[2]is set high to turn the transistor 110[2] on. The potential of thewiring VIN is thus supplied to the wiring SE[2], and the potential ofthe wiring SE[2] becomes high.

Although the potential of the wiring OUT is controlled by changing thepotential of the wiring BR in this example, a predetermined potentialmay be continuously supplied to wiring BR. In that case, the transistor120 serves as a current source and the potential of the wiring OUT isdetermined in accordance with the potential of the wiring BR.

In this example, the wiring SE[2] serves as a power source line for thepixels 21[2,1] and 21[2,2]. Specifically, the potential of the wiringSE[2] is supplied to the transistor 104 serving as an amplifiertransistor. Accordingly, the potentials of the wirings OUT[1] and OUT[2]become potentials corresponding to the potentials of the nodes FN[2,1]and FN[2,2], respectively. The potentials of the wirings OUT[1] andOUT[2] correspond to optical data signals of the pixels 21[2,1] and21[2,2], respectively. The transistor 110[2] in the period T11 serves asa selection transistor for selecting the pixels 21 from which an opticaldata signal is read.

In addition, the pixels 21[1,1] and 21[1,2] are reset in the period T11.Specifically, the nodes FN[1,1] and FN[1,2] are low and the transistors104 of the pixels 21[1,1] and 21[1,2] are off; accordingly, the wiringSE[1] is not electrically connected to the wirings OUT[1] and OUT[2].This can suppress potential changes of the wirings OUT[1] and OUT[2]caused by the potential of the wiring SE[1] when optical data signalsare read from the pixels 21[2,1] and 21[2,2].

Next, in a period T12, the potential of the wiring CSE[2] is set low toturn the transistor 110[2] off. The supply of power source potential tothe wiring SE[2] is accordingly stopped, and the reading of optical datasignals ends.

Through the operation, reset, light exposure and reading are performedin the second-row pixels.

Then, in a period T13, the potential of the wiring PR is set high toturn on the transistors 103 in all of the pixels 21, and the potentialof the node FN is reset low. Through the operation similar to thatdescribed above, light exposure and reading are performed in pixels 21in the third row and subsequent rows and reset, light exposure, andreading are performed in pixels 21 in the fourth rows and subsequentrows.

As described, in one embodiment of the present invention, the switchesfor selecting the pixels 21 are shared by the pixels 21 in one row andare provided outside the pixel portion 20. Thus, a switch for selectingthe pixels 21 and a power source line connected to the switch need notbe provided in the pixel portion 20, which leads to the reduction in thearea of the pixel portion 20.

In addition, in one embodiment of the present invention, the wiring VINfunctioning as a power source line for selecting the pixels 21 isprovided outside the pixel portion 20. Thus, if the wiring VIN is formedusing a wiring different from a wiring (e.g., the wiring VPR) connectedto the pixels 21, the area of the pixel portion 20 is not increased.Since a potential different from that supplied to the power source lineconnected to the pixels 21 can be thus supplied to the wiring VIN, apower potential used for reading an optical data signal can be freelydetermined, which leads to an improvement of the freedom degree ofdesign and the versatility of the semiconductor device 10.

In this embodiment, embodiments of the present invention are described.Note that one embodiment of the present invention is not limited tothem. In other words, since various embodiments of the invention aredescribed in this embodiment, one embodiment of the present invention isnot limited to a particular embodiment. For example, one embodiment ofthe present invention is not limited to the above-described example of asemiconductor device in which a switch that is shared by pixels in onerow is provided outside a pixel portion. Depending on circumstances orsituations, one embodiment of the present invention may include astructure in which the switch is not shared by pixels in one row or theswitch is provided inside the pixel portion. In addition, one embodimentof the present invention is not limited to the above-described exampleof a semiconductor device in which a power source line connected to ashared switch is different from a power source line connected to pixels.Depending on circumstances or situations, one embodiment of the presentinvention may include a structure in which these power source lines arethe same line.

Although light exposure is performed row by row in this embodiment, aglobal shutter system that performs light exposure in pixels 21 inseveral rows (pixels 21 in all the rows at a maximum) at the same timeand then performs row-by-row reading sequentially can be employed, inwhich case distortion-free images can be obtained. However, in a globalshutter system, time from exposure to reading, i.e., a period whencharge is retained in the node FN, varies depending on the row where thepixels 21 are provided. Therefore, potential change of the node FNcaused by time passage is preferably small when a global shutter systemis employed. Here, if an OS transistor is used in the pixel 21, chargestored in the node FN can be retained for an extremely long time;therefore, an optical data signal can be accurately read even when aglobal shutter system is employed.

This embodiment can be combined with any other embodiment asappropriate. Content (or may be part of the content) described in oneembodiment may be applied to, combined with, or replaced by differentcontent (or may be part of the different content) described in theembodiment and/or content (or may be part of the content) described inone or more different embodiments. Note that in each embodiment, acontent described in the embodiment is a content described withreference to a variety of diagrams or a content described with a textdescribed in this specification. In addition, by combining a diagram (orpart thereof) described in one embodiment with another part of thediagram, a different diagram (or part thereof) described in the sameembodiment, and/or a diagram (or part thereof) described in another orother embodiments, much more diagrams can be formed. The same can beapplied to any other embodiment

Embodiment 2

In this embodiment, structure examples of a pixel of one embodiment ofthe present invention are described.

<Layout Example of Pixels>

FIG. 5 is a layout example of the pixel 21, which can be used in theabove embodiment. Note that the wirings, conductive layers, andsemiconductor layers using the same hatch pattern in FIG. 5 can beformed using the same material in the same process.

The pixel 21 in FIG. 5 includes the transistors 102, 103, and 104 andthe capacitor 105. Detailed description of connection relationshipbetween the elements is skipped because the description of FIG. 2 can bereferred to. Although the photoelectric conversion element 101 is notshown in FIG. 5, the photoelectric conversion element 101 is connectedto a conductive layer 250.

A semiconductor layer 221 serves as an active layer of the transistors102 and 103. That is, the semiconductor layer 221 is shared by thetransistors 102 and 103. A semiconductor layer 222 serves as an activelayer of the transistor 104.

The semiconductor layer 221 is connected to conductive layers 231 and232. The conductive layer 231 is connected to a conductive layer 250through an opening 251. The conductive layer 232 is connected to aconductive layer 212 through an opening 253. The semiconductor layer 221is connected to a conductive layer 243 through an opening 255.

The conductive layer 231 functions as the one of the source and drain ofthe transistor 102. The conductive layer 232 functions as the one of thesource and drain of the transistor 103. The conductive layer 243functions as the other of the source and drain of the transistor 102,the other of the source and drain of the transistor 103, the gate of thetransistor 104, and the one electrode of the capacitor 105.

The semiconductor layer 222 is connected to conductive layers 233 and234. The conductive layer 233 is connected to a conductive layer 202through an opening 256. The conductive layer 234 is connected to aconductive layer 211 through an opening 257.

The conductive layer 233 functions as the one of the source and drain ofthe transistor 104. The conductive layer 234 functions as the other ofthe source and drain of the transistor 104.

The conductive layers 212, 202, and 211 correspond to the wirings VPR,SE, and OUT, respectively. A node connected to the semiconductor layer221 and the conductive layer 243 corresponds to the node FN.

Single crystal semiconductor layers, non-single crystal semiconductorlayers, and the like can be used as the semiconductor layers 221 and222, and an oxide semiconductor layer is preferably used, in which casethe transistors 102 to 104 become OS transistors.

A conductive layer 241 is connected to the conductive layer 203 throughan opening 252. The conductive layer 241 serves as the gate of thetransistor 102. Note that the conductive layer 241 may be included inthe conductive layer 203. The conductive layer 203 corresponds to thewiring TX.

A conductive layer 242 is connected to the conductive layer 204 throughan opening 254. The conductive layer 242 serves as the gate of thetransistor 103. Note that the conductive layer 242 may be included inthe conductive layer 204. The conductive layer 204 corresponds to thewiring PR.

A conductive layer 201 includes a region overlapping with the conductivelayer 243 with an insulating layer provided therebetween (not shown).The conductive layer 201 serves as the other electrode of the capacitor105 and corresponds to the wiring VPD.

Although each of the transistors 102 to 104 in FIG. 5 is a top-gatetransistor, each of them may be a top-gate transistor or a bottom-gatetransistor.

Although the semiconductor layers 221 and 222, the conductive layers 231to 234, the conductive layers 241 to 243, the conductive layers 211 and212, the conductive layers 201 to 204, and the conductive layer 250 arestacked in this order in FIG. 5, their stacking order can be freelydetermined without limitation thereto.

<Modification Example of Pixel>

Next, a modification example of the pixel 21, which is described inEmbodiment 1, is shown.

The pixel 21 may have a configuration illustrated in FIG. 6A. The pixel21 in FIG. 6A differs from that in FIG. 2 in that the anode and thecathode of the photoelectric conversion element 101 are respectivelyconnected to the wiring VPD and one of the source and drain of thetransistor 102. In FIG. 6A, the wirings VPD and VPR are a low-potentialpower source line and a high-potential power source line, respectively.

Note that in one embodiment of the present invention, the transistor 104is preferably turned off by the supply of the potential of the wiringVPR as a reset potential to the node FN. Accordingly, it is preferablethat the transistor 104 be a p-channel transistor in FIG. 6A and beturned off by the supply of a high-level potential from the wiring VPRto the node FN.

Further, the pixel 21 may have a configuration illustrated in FIG. 6B.The pixel 21 shown in FIG. 6B is different from the structure in FIG. 2in that a plurality of photoelectric conversion elements 101 and aplurality of transistors 102 are included. A first terminal and a secondterminal of a photoelectric conversion element 101 a are connected toone of a source and drain of a transistor 102 a and the wiring VPD,respectively. A first terminal and a second terminal of a photoelectricconversion element 101 b are connected to one of a source and drain of atransistor 102 b and the wiring VPD, respectively. A gate of thetransistor 102 a and a gate of the transistor 102 b are connected to awiring TXa and a wiring TXb, respectively. The other of the source anddrain of the transistor 102 a and the other of the source and drain ofthe transistor 102 b are connected to the node FN.

The gate of the transistor 102 a and the gate of the transistor 102 bare connected to the different wirings, whereby exposure by thephotoelectric conversion element 101 a and that by the photoelectricconversion element 101 b are separately controlled. With such astructure, exposure can be performed with the use of the twophotoelectric conversion elements in one pixel. Note that there is noparticular limitation on the number of the photoelectric conversionelements provided in the pixel 21, and three or more photoelectricconversion elements may be provided.

The pixel 21 may have a configuration illustrated in FIG. 6C. In thecircuit configuration in FIG. 6C, the transistor 103 is omitted from thecircuit in FIG. 2. The anode and the cathode of the photoelectricconversion element 101 are connected to one of the source and drain ofthe transistor 102 and the wiring VPR, respectively.

In order to reset the pixel 21 (this operation corresponds to theoperation in the periods T1 and T7 shown in FIG. 4, for example), thepotentials of the wirings VPR and TX are set low and high, respectively.The forward bias is accordingly applied to the photoelectric conversionelement 101 to reset the potential of the node FD to low. After thereset of the node FD, the potential of the wiring VPR is set high.

The pixel 21 may have a configuration illustrated in FIG. 6D. The pixel21 in FIG. 6D differs from the pixel 21 in FIG. 6C in that the anode andthe cathode of the photoelectric conversion element 101 are connected tothe wiring VPD and one of the source and drain of the transistor 102,respectively.

In order to reset the pixel 21 (this operation corresponds to theoperation in the periods T1 and T7 shown in FIG. 4, for example), thepotentials of the wirings VPR and TX are set high. The forward bias isaccordingly applied to the photoelectric conversion element 101 to resetthe potential of the node FD to high. After the reset of the node FD,the potential of the wiring VPR is set low.

Note that in one embodiment of the present invention, the transistor 104is preferably turned off by the supply of the potential of the wiringVPR as a reset potential to the node FN. Accordingly, it is preferablethat the transistor 104 be a p-channel transistor in FIG. 6D and beturned off by the reset of the potential of the node FN to high.

The transistor 102 can be omitted from FIG. 2. FIGS. 7A and 7B showconfigurations in which the transistor 102 is omitted from FIG. 2 andFIG. 6A, respectively.

A transistor used for the pixel 21 may include a second gate electrode(hereinafter, also referred to as a back gate) in addition to a firstgate electrode (hereinafter, also referred to as a front gate). FIGS. 8Ato 8D show configurations in which each of the transistors 102, 103, and104 includes a back gate.

FIG. 8A shows a configuration in which each of the transistors 102, 103,and 104 shown in FIG. 2 includes a back gate connected to a front gateso that the same potential can be supplied to the back gate and thefront gate. FIG. 8B shows a configuration in which each of thetransistors 102, 103, and 104 shown in FIG. 6A includes a back gateconnected to a front gate so that the same potential can be supplied tothe back gate and the front gate. Such configurations can increaseon-state current of the transistors 102, 103, and 104, leading tohigh-speed image taking.

FIG. 8C is a configuration in which each of the transistors 102, 103,and 104 in FIG. 2 includes a back gate connected to the wiring VPR sothat a constant potential can be supplied to the back gate. A groundpotential is supplied to the wiring VPR in FIG. 8C. FIG. 8D is aconfiguration in which each of the transistors 102, 103, and 104 in FIG.6A includes a back gate connected to the wiring VPD so that a constantpotential can be supplied to the back gate. A ground potential issupplied to the wiring VPD in FIG. 8D. Such configurations can controlthreshold voltages of the transistors 102, 103, and 104, leading tohighly reliable image taking.

Although each of the back gates of the transistors 102, 103, and 104 isconnected to the wiring VPR in FIG. 8C and each of the back gates of thetransistors 102, 103, and 104 is connected to the wiring VPD in FIG. 8D,the back gates may be connected to other wirings to which a constantpotential is supplied. A back gate can be provided similarly in thepixels 21 shown in FIGS. 6B to 6D and FIGS. 7A and 7B.

As each of the transistors 102, 103, and 104, any of a transistor inwhich the same potential is supplied to a back gate and a front gate, atransistor in which a constant potential is supplied to a back gate, anda transistor in which a back gate is not provided can be used. In otherwords, one pixel 21 can include two or more different kinds oftransistors.

In FIG. 2, FIGS. 6A to 6D, FIGS. 7A and 7B, and FIGS. 8A to 8D, elementsincluded in the pixel 21 can be shared by a plurality of pixels. FIG. 9shows a structure of the pixel portion 20 in which the transistors 103and 104 and the capacitor 105 in FIG. 2 are shared by four pixels 21. InFIG. 9, the four transistors 102 are connected to the node FN, and thenode FN is connected to the transistors 103 and 104 and the capacitor105. Such a structure can reduce the number of elements in the pixelportion 20.

Although a transistor and a capacitor are shared by pixels 21 indifferent rows in FIG. 9, a transistor and/or a capacitor may be sharedby pixels 21 in different columns. In addition, although the transistors103 and 104 and the capacitor 105 are shared by four pixels, the numberof pixels sharing the elements is not limited to four and may be two,three, five, or more. The same applies to the pixels 21 in FIGS. 6A to6D, FIGS. 7A and 7B, FIGS. 8A to 8D.

The configurations shown in FIG. 2, FIGS. 6A to 6D, FIGS. 7A and 7B,FIGS. 8A to 8D, and FIG. 9 can be freely combined.

This embodiment can be combined with any other embodiment asappropriate.

Embodiment 3

In this embodiment, an imaging device including the semiconductor deviceof one embodiment of the present invention is described.

FIG. 10 illustrates a structure example of an imaging device 300. Theimaging device 300 includes a photodetector portion 310 and a dataprocessing portion 320.

The photodetector portion 310 includes circuits 20, 30, 40, 50, and 60.The pixel portion and the circuit described in the above embodiments canbe used for the pixel portion 20 and the circuits 30 and 40.

The circuit 50 has a function of converting an analog signal input fromthe circuit 40 into a digital signal. The circuit 50 can be composed ofan A/D converter and the like.

The circuit 60 is a driving circuit having a function of reading adigital signal input from the circuit 50. The circuit 60 includes aselection circuit. The selection circuit can be formed using atransistor. The transistor can be an OS transistor or the like.

The data processing portion 320 includes a circuit 321. The circuit 321has a function of generating image data with the use of the digitalsignal corresponding to the difference data generated in thephotodetector portion 310.

The circuit 20 may include a circuit having a function of displaying animage. With such a structure, the imaging device 300 can serve as atouch panel.

Next, an example of a driving method of the imaging device 300 in FIG.10 is described.

First, an optical data signal is generated in the pixels 21 in a mannerdescribed in Embodiment 1. The optical data signal generated in thepixels 21 is output to the circuit 40. Then, the circuit 40 converts theoptical data signal into an analog signal and outputs to the circuit 50.

The analog signal output from the circuit 40 is converted into a digitalsignal in the circuit 50, and the digital signal is output to thecircuit 60. The circuit 60 reads the digital signal. The digital signalread in the circuit 60 is used for processing in the circuit 321 and thelike.

This embodiment can be combined with any other embodiment asappropriate.

Embodiment 4

In this embodiment, structure examples of an element that can be used inthe semiconductor device 10 are described.

FIGS. 11A to 11C show structure examples of transistors and aphotoelectric conversion element that can be used in the semiconductordevice 10. A photodiode is used as the photoelectric conversion element,as an example, in this embodiment.

<Structure Example 1>

FIG. 11A shows a structure example of a transistor 801, a transistor802, and a photodiode 803. The transistor 801 is connected to thetransistor 802 through a wiring 819 and a conductive layer 823, and thetransistor 802 is connected to the photodiode 803 through a conductivelayer 830.

The transistors 801 and 802 can be freely used as the transistors shownin FIG. 2, FIG. 3, FIGS. 6A to 6D, FIGS. 7A and 7B, FIGS. 8A to 8D, andFIG. 9 and other transistors included in the semiconductor device 10.For example, the transistor 801 the transistor 802 can be used as thetransistors 110 and 120 and the like in FIG. 2 and FIG. 3, thetransistor 102 to 104 and the like in FIG. 2, FIG. 3, FIGS. 6A to 6D,FIGS. 7A and 7B, FIGS. 8A to 8D, and FIG. 9, respectively. Thephotodiode 803 can be used as the photoelectric conversion element 101in FIG. 2, FIG. 3, FIGS. 6A to 6D, FIGS. 7A and 7B, FIGS. 8A to 8D, andFIG. 9.

[Transistor 801]

First, the transistor 801 is described.

The transistor 801 is formed using a semiconductor substrate 810 andincludes element separation layers 811 over the semiconductor substrate810 and impurity regions 812 formed in the semiconductor substrate 810.The impurity regions 812 have a function as a source region and a drainregion of the transistor 801, and a channel region is formed between theimpurity regions 812. The transistor 801 further includes an insulatinglayer 813 and a conductive layer 814. The insulating layer 813 has afunction as a gate insulating layer of the transistor 801, and theconductive layer 814 has a function as a gate electrode of thetransistor 801. Note that a side wall 815 may be formed on the sidesurface of the conductive layer 814. Furthermore, an insulating layer816 having a function as a protective layer and an insulating layer 817having a function as a planarization film can be formed over theconductive layer 814.

A silicon substrate is used as the semiconductor substrate 810. Notethat germanium, silicon germanium, silicon carbide, gallium arsenide,aluminum gallium arsenide, indium phosphide, gallium nitride, or anorganic semiconductor besides silicon can be used as a material of thesubstrate.

The element separation layer 811 can be formed by a local oxidation ofsilicon (LOCOS) method, a shallow trench isolation (STI) method, or thelike.

The impurity regions 812 include an impurity element impartingconductivity to the material of the semiconductor substrate 810. When asilicon substrate is used as the semiconductor substrate 810,phosphorus, arsenic, or the like is used as the impurity impartingn-type conductivity; and boron, aluminum, gallium, or the like is usedas the impurity imparting p-type conductivity. The impurity element canbe added to a predetermined region of the semiconductor substrate 810 byan ion implantation method, an ion doping method, or the like.

The insulating layer 813 can be formed using an insulating layercontaining at least one of aluminum oxide, magnesium oxide, siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.Alternatively, the insulating layer 813 may be formed using stackedinsulating layers each containing one or more of the above materials.

The conductive layer 814 can be formed using a conductive film ofaluminum, titanium, chromium, cobalt, nickel, copper, yttrium,zirconium, molybdenum, silver, manganese, tantalum, tungsten, or thelike. It is also possible to use an alloy or conductive nitride of anyof these materials. It is also possible to use a stack of a plurality ofmaterials selected from these materials, alloys of these materials, andconductive nitride of these materials.

The insulating layer 816 can be formed using an insulating layercontaining at least one of magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, and tantalum oxide. Alternatively, theinsulating layer 816 may be formed using stacked insulating layers eachcontaining one or more of the above materials.

An organic material such as an acrylic resin, an epoxy resin, abenzocyclobutene resin, polyimide, or polyamide can be used for theinsulating layer 817. Alternatively, the insulating layer 817 may beformed using stacked insulating layers each containing one or more ofthe above materials. A material similar to the material of theinsulating layer 816 can be used for the insulating layer 817.

Note that the impurity region 812 can be connected to the wiring 819 viaa conductive layer 818.

[Transistor 802]

Next, the transistor 802 is described. The transistor 802 is an OStransistor.

The transistor 802 includes an oxide semiconductor layer 824 over aninsulating layer 822, conductive layers 825 over the oxide semiconductorlayer 824, an insulating layer 826 over the conductive layers 825, and aconductive layer 827 over the insulating layer 826. The conductivelayers 825 have a function as a source electrode and a drain electrodeof the transistor 802. The insulating layer 826 has a function as a gateinsulating layer of the transistor 802. The conductive layer 827 has afunction as a gate electrode of the transistor 802. Furthermore, aninsulating layer 828 having a function as a protective layer and aninsulating layer 829 having a function as a planarization film can beformed over the conductive layer 827.

A conductive layer 821 may be formed under the insulating layer 822. Inthat case, the conductive layer 821 has a function as a back gateelectrode of the transistor 802. In the case where the conductive layer821 is formed, the conductive layer 821 can be formed over theinsulating layer 820 that is formed over the wiring 819. Alternatively,part of the wiring 819 may serve as a back gate electrode of thetransistor 802. An OS transistor with a back gate electrode can be usedfor the transistors 102 to 104 in FIGS. 8A to 8D.

When a transistor T includes a pair of gates that sandwiches asemiconductor film as in the transistor 802, one of the gates may besupplied with a signal A and the other of the gates may be supplied witha fixed potential Vb.

The signal A is, for example, a signal for controlling the on/off state.The signal A may be a digital signal with two kinds of potentials, V1and V2 (V1>V2). For example, the potential V1 may be a high power sourcepotential and the potential V2 may be a low power source potential. Thesignal A may be an analog signal.

The fixed potential Vb is, for example, a potential for controlling athreshold voltage VthA of the transistor T. The fixed potential Vb maybe the potential V1 or the potential V2. In that case, a potentialgenerator circuit for generating the fixed potential Vb is notnecessary, which is preferable. The fixed potential Vb may be differentfrom the potential V1 or the potential V2. When the fixed potential Vbis low, the threshold voltage VthA can be increased in some cases. As aresult, a drain current of when a voltage Vgs between the gate and asource is 0 V can be reduced and a leakage current of the circuitincluding the transistor T can be reduced in some cases. The fixedpotential Vb may be, for example, lower than the low power sourcepotential. When the fixed potential Vb is high, the threshold voltageVthA may be decreased in some cases. As a result, a drain current ofwhen the voltage Vgs between the gate and the source is VDD can beincreased and operation speed of the circuit including the transistor Tcan be increased in some cases. The fixed potential Vb may be, forexample, higher than the low power source potential.

The signal A and a signal B may be applied to one gate and the othergate of the transistor T, respectively. The signal B is, for example, asignal for controlling the on/off state of the transistor T. The signalB may be a digital signal with two kinds of potentials, V3 and V4(V3>V4). For example, the potential V3 may be the high power sourcepotential and the potential V4 may be the low power source potential.The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signalB may have the same digital value as the signal A. In that case, anon-state current of the transistor T may be increased and operationspeed of the circuit including the transistor T may be increased in somecases. Here, the potential V1 of the signal A may be different from thepotential V3 of the signal B, and the potential V2 of the signal A maybe different from the potential V4 of the signal B. For example, if agate insulating film used with the gate to which the signal B is inputis thicker than a gate insulating film used with the gate to which thesignal A is input, the potential amplitude of the signal B (V3−V4) canbe larger than the potential amplitude of the signal A (V1−V2). In thisway, influence of the signal A and that of the signal B on the on/offstate of the transistor T can be approximately the same in some cases.

When both the signal A and the signal B are digital signals, the signalB may be a signal with a different digital value from that of the signalA. In that case, the signal A and the signal B can separately controlthe transistor T, and thus higher performance may be achieved. Forexample, if the transistor T is an n-channel transistor, the transistorT may be turned on only when the signal A has the potential V1 and thesignal B has the potential V3, or may be turned off only when the signalA has the potential V2 and the signal B has the potential V4, in whichcase the transistor T, a single transistor, may function as a NANDcircuit, a NOR circuit, or the like. In addition, the signal B may be asignal for controlling the threshold voltage VthA. For example, thepotential of the signal B in a period when the circuit including thetransistor T operates may be different from the potential of the signalB in a period when the circuit does not operate. The potential of thesignal B may vary depending on operation modes of the circuit. In thatcase, the potential of the signal B is not switched so often as that ofthe signal A in some cases.

When both the signal A and the signal B are analog signals, the signal Bmay be an analog signal with the same potential as that of the signal A,an analog signal with a potential that is a constant multiple of thepotential of the signal A, an analog signal with a potential that ishigher or lower than the potential of the signal A by a constant, or thelike. In that case, an on-state current of the transistor T may beincreased and operation speed of the circuit including the transistor Tmay be increased in some cases. The signal B may be an analog signaldifferent from the signal A. In that case, the signal A and the signal Bcan separately control the transistor T, and thus higher performance maybe achieved.

The signal A and the signal B may be a digital signal and an analogsignal, respectively. The signal A and the signal B may be an analogsignal and a digital signal, respectively.

A fixed potential Va and a fixed potential Vb may be applied to one gateand the other gate of the transistor T, respectively. When both of thegates of the transistor T are supplied with the fixed potentials, thetransistor T can serve as an element equivalent to a resistor in somecases. For example, when the transistor T is an n-channel transistor,effective resistance of the transistor can be decreased (increased) byheightening (lowering) the fixed potential Va or the fixed potential Vbin some cases. When both the fixed potential Va and the fixed potentialVb are heightened (lowered), effective resistance lower (higher) thanthat obtained by the transistor with one gate can be obtained in somecases.

The insulating layer 822 can be formed using an insulating layercontaining at least one of magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, and tantalum oxide. Alternatively, theinsulating layer 822 may be formed using stacked insulating layers eachcontaining one or more of the above materials. Note that it ispreferable that the insulating layer 822 have a function of supplyingoxygen to the oxide semiconductor layer 824. This is because even in thecase where oxygen vacancies are present in the oxide semiconductor layer824, the oxygen vacancies are repaired by oxygen supplied from theinsulating layer. An example of treatment for supplying oxygen is heattreatment.

An oxide semiconductor layer can be used for the oxide semiconductorlayer 824. As an oxide semiconductor, for example, any of the followingcan be used: indium oxide, tin oxide, gallium oxide, zinc oxide, In—Znoxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, Sn—Mg oxide, In—Mg oxide,In—Ga oxide, In—Ga—Zn oxide, In—Al—Zn oxide, In—Sn—Zn oxide, Sn—Ga—Znoxide, Al—Ga—Zn oxide, Sn—Al—Zn oxide, In—Hf—Zn oxide, In—La—Zn oxide,In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In—Sm—Zn oxide, In—Eu—Znoxide, In—Gd—Zn oxide, In—Tb—Zn oxide, In—Dy—Zn oxide, In—Ho—Zn oxide,In—Er—Zn oxide, In—Tm—Zn oxide, In—Yb—Zn oxide, In—Lu—Zn oxide,In—Sn—Ga—Zn oxide, In—Hf—Ga—Zn oxide, In—Al—Ga—Zn oxide, In—Sn—Al—Znoxide, In—Sn—Hf—Zn oxide, and In—Hf—Al—Zn oxide. In particular, In—Ga—Znoxide is preferable.

Here, In—Ga—Zn oxide means oxide containing In, Ga, and Zn as its maincomponents. Note that a metal element other than In, Ga, and Zn may becontained as an impurity. Note that a film formed using In—Ga—Zn oxideis also referred to as an IGZO film.

The conductive layer 825 can be formed using a conductive film ofaluminum, titanium, chromium, cobalt, nickel, copper, yttrium,zirconium, molybdenum, silver, manganese, tantalum, tungsten, or thelike. It is also possible to use an alloy or conductive nitride of anyof these materials. It is also possible to use a stack of a plurality ofmaterials selected from these materials, alloys of these materials, andconductive nitride of these materials. Typically, it is preferable touse titanium, which is particularly easily bonded to oxygen, ortungsten, which has a high melting point and thus allows subsequentprocess temperatures to be relatively high. It is also possible to use astack of any of the above materials and copper or an alloy such ascopper-manganese, which has low resistance. When a material which iseasily bonded to oxygen is used for the conductive layer 825, and theconductive layer 825 and the oxide semiconductor layer 824 are incontact with each other, a region including oxygen vacancies is formedin the oxide semiconductor layer 824. Hydrogen slightly contained in thefilm is diffused into the oxygen vacancies, whereby the region ismarkedly changed to an n-type region. The n-type region can function asa source region or a drain region of the transistor.

The insulating layer 826 can be formed using an insulating layercontaining at least one of aluminum oxide, magnesium oxide, siliconoxide, silicon oxynitride, silicon nitride oxide, silicon nitride,gallium oxide, germanium oxide, yttrium oxide, zirconium oxide,lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.Alternatively, the insulating layer 826 may be formed using stackedinsulating layers each containing one or more of the above materials.

The conductive layer 827 can be formed using a conductive film ofaluminum, titanium, chromium, cobalt, nickel, copper, yttrium,zirconium, molybdenum, silver, manganese, tantalum, tungsten, or thelike. It is also possible to use an alloy or conductive nitride of anyof these materials. It is also possible to use a stack of a plurality ofmaterials selected from these materials, alloys of these materials, andconductive nitride of these materials.

The insulating layer 828 can be formed using an insulating filmcontaining at least one of magnesium oxide, silicon oxide, siliconoxynitride, silicon nitride oxide, silicon nitride, gallium oxide,germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, and tantalum oxide. Alternatively, theinsulating layer 828 may be formed using stacked insulating layers eachcontaining one or more of the above materials.

An organic material such as an acrylic resin, an epoxy resin, abenzocyclobutene resin, polyimide, or polyamide can be used for theinsulating layer 829. Alternatively, the insulating layer 817 may beformed using stacked insulating layers each containing one or more ofthe above materials. A material similar to the material of theinsulating layer 828 can be used for the insulating layer 829.

[Photodiode 803]

Next, the photodiode 803 is described.

In the photodiode 803, an n-type semiconductor layer 832, an i-typesemiconductor layer 833, and a p-type semiconductor layer 834 arestacked in this order. The i-type semiconductor layer 833 is preferablyformed using amorphous silicon. Furthermore, the n-type semiconductorlayer 832 and the p-type semiconductor layer 834 can be formed usingamorphous silicon or microcrystalline silicon including an impurityimparting conductivity. A photodiode using amorphous silicon ispreferable because its sensitivity in a wavelength region of visiblelight is high. Note that the p-type semiconductor layer 834 serves as alight-receiving surface, whereby the output current of the photodiodecan be increased.

The n-type semiconductor layer 832 having a function as a cathode isconnected to the conductive layer 825 of the transistor 802 via theconductive layer 830. Furthermore, the p-type semiconductor layer 834having a function as an anode is connected to a wiring 837. Thephotodiode 803 may be connected to another wiring via a wiring 831 or aconductive layer 836. Furthermore, an insulating layer 835 having afunction as a protective film can be formed.

The stacked structure shown in FIG. 11A in which the transistor 802 isover the transistor 801 and the photodiode 803 is over the transistor802 can reduce the area of the semiconductor device.

Although the impurity region 812 is connected to the conductive layer825 in FIG. 11A, that is, a gate of the transistor 801 is connected toone of a source and a drain of the transistor 802, the connectionrelation between the transistor 801 and the transistor 802 is notlimited thereto. For example, as shown in FIG. 11B, the conductive layer814 may be connected to the conductive layer 825, that is, one of asource and a drain of the transistor 801 may be connected to one of thesource and the gate of the transistor 802.

Although not illustrated, the gate of the transistor 801 may beconnected to a gate of the transistor 802, or one of the source anddrain of the transistor 801 may be connected to the gate of thetransistor 802.

Alternatively, as shown in FIG. 11C, the OS transistor may be omittedand the photodiode 803 may be connected to the transistor 801. Thestructure shown in FIG. 11C can be used when all the transistors in FIG.2 is single-crystal transistors, for example. The number of steps ofmanufacturing the semiconductor device can be reduced by omission of theOS transistor.

<Structure Example 2>

Although the photodiode 803 is stacked over the transistor 802 in FIGS.11A to 11C, the position of the photodiode 803 is not limited thereto.For example, as shown in FIG. 12A, the photodiode 803 may be providedbetween the transistor 801 and the transistor 802.

Alternatively, as shown in FIG. 12B, the photodiode 803 may be providedin the layer where the transistor 802 is provided. In that case, theconductive layer 825 may be used as the source electrode or the drainelectrode of the transistor 802 and an electrode of the photodiode 803.

Alternatively, as shown in FIG. 12C, the photodiode 803 may be providedin the layer where the transistor 801 is provided. In that case, theconductive layer 814 having a function as the gate electrode of thetransistor 801 and the wiring 831 having a function as the electrode ofthe photodiode 803 may be formed with the same material at a time.

A plurality of transistors can be formed using the semiconductorsubstrate 810. FIG. 13A shows an example where a transistor 804 and atransistor 805 are formed using the semiconductor substrate 810.

The transistor 804 includes impurity regions 842, an insulating layer843 having a function as a gate insulating film, and a conductive layer844 having a function as a gate electrode. The transistor 805 includesimpurity regions 852, an insulating film 853 having a function as a gateinsulating film, and a conductive layer 854 having a function as a gateelectrode. Structures and materials of the transistors 804 and 805 arethe same as those of the transistor 801, and thus the detaileddescription is omitted.

The impurity regions 842 include an impurity element imparting oppositeconductivity type to conductivity type of the impurity regions 852. Thatis, the transistor 804 has an opposite polarity to the polarity of thetransistor 805. In addition, as shown in FIG. 13A, the impurity region842 may be connected to the impurity region 852. In that case, acomplementary metal oxide semiconductor (CMOS) inverter including thetransistor 804 and the transistor 805 can be formed.

The circuits 30, 40, 50, and 60 and the data processing portion 320 inFIG. 1 and FIG. 10 include the transistor using the semiconductorsubstrate 810, and then the pixel portion 20 including OS transistorscan be stacked over the circuits. The structure shown in FIG. 13A canreduce the area of the semiconductor device.

In a structure where a transistor 807 that is an OS transistor isstacked over a transistor 806 formed using the semiconductor substrate810 as shown in FIG. 13B, an impurity region 861 may be connected to aconductive layer 862, that is, a source or a drain of the transistor 806may be connected to a source or a drain of the transistor 807. In thisway, a CMOS inverter including the transistor formed using thesemiconductor substrate 810 and the OS transistor can be formed.

The transistor 806 formed using the semiconductor substrate 810 iseasily formed to be a p-channel transistor as compared with the OStransistor. Therefore, it is preferable that the transistor 806 be ap-channel transistor and the transistor 807 be an n-channel transistor.In this way, a CMOS inverter can be formed without formation of twokinds of transistors with different polarities using the semiconductorsubstrate 810, whereby the manufacturing steps of the semiconductordevice can be reduced.

This embodiment can be combined with any other embodiment asappropriate.

Embodiment 5

In this embodiment, a structure example of an imaging device to which acolor filter and the like are added is described.

FIG. 14A is a cross-sectional view of an example of an embodiment inwhich a color filter and the like are added to the structure in any ofFIGS. 11A to 11C, FIGS. 12A to 12C, FIGS. 13A and 13B, and the like, andillustrates a region occupied by circuits (pixels 21 a, 21 b, and 21 c)corresponding to three pixels. An insulating layer 1500 is formed overthe photodiode 803 provided in the layer 1100. As the insulating layer1500, for example, a silicon oxide film with a high visible-lighttransmitting property can be used. In addition, a silicon nitride filmmay be stacked as a passivation film. In addition, a dielectric film ofhafnium oxide or the like may be stacked as an anti-reflection film.

A light-blocking layer 1510 is formed over the insulating layer 1500.The light-blocking layer 1510 has a function of inhibiting color mixingof light passing through the color filter. The light-blocking layer 1510can be formed using a metal layer of aluminum, tungsten, or the like, ora stack including the metal layer and a dielectric film functioning asan anti-reflection film.

An organic resin layer 1520 is formed as a planarization film over theinsulating layer 1500 and the light-blocking layer 1510. A color filter1530 a, a color filter 1530 b, and a color filter 1530 c are formed overthe pixel 21 a, the pixel 21 b, and the pixel 21 c to be paired up withthe pixel 21 a, the pixel 21 b, and the pixel 21 c, respectively. Thecolor filter 1530 a, the color filter 1530 b, and the color filter 1530c have colors of R (red), G (green), B (blue), and the like, whereby acolor image can be obtained.

A microlens array 1540 is provided over the color filters 1530 a, 1530b, and 1530 c so that light penetrating a lens goes through the colorfilter positioned just below the lens to reach the photodiode.

A supporting substrate 1600 is provided in contact with the layer 1400.As the supporting substrate 1600, a hard substrate such as asemiconductor substrate (e.g., a silicon substrate), a glass substrate,a metal substrate, or a ceramic substrate can be used. Note that aninorganic insulating layer or an organic resin layer as an adheringlayer may be between the layer 1400 and the supporting substrate 1600.

In the structure of the imaging device, an optical conversion layer 1550(see FIG. 14B) may be used instead of the color filters 1530 a, 1530 b,and 1530 c. When the optical conversion layer 1550 is used instead, theimaging device can convert light in various wavelength regions into animage.

For example, when a filter which blocks light having a wavelengthshorter than or equal to that of visible light is used as the opticalconversion layer 1550, an infrared imaging device can be obtained. Whena filter which blocks light having a wavelength shorter than or equal tothat of near infrared light is used as the optical conversion layer1550, a far-infrared imaging device can be obtained. When a filter whichblocks light having a wavelength longer than or equal to that of visiblelight is used as the optical conversion layer 1550, an ultravioletimaging device can be obtained.

Furthermore, when a scintillator is used as the optical conversion layer1550, an imaging device which takes an image visualizing the intensityof a radiation, such as a medical X-ray imaging device, can be obtained.Radiations such as X-rays passes through a subject to enter ascintillator, and then is converted into light (fluorescence) such asvisible light or ultraviolet light owing to a phenomenon known asphotoluminescence. Then, the photodiode 803 detects the light to obtainimage data.

The scintillator is formed of a substance that, when irradiated withradiations such as X-rays or gamma-rays, absorbs energy of theradiations to emit visible light or ultraviolet light or a materialcontaining the substance. For example, materials such as Gd₂O₂S:Tb,Gd₂O₂S:Pr, Gd₂O₂S:Eu, BaFCl:Eu, NaI, CsI, CaF₂, BaF₂, CeF₃, LiF, LiI,and ZnO and a resin or ceramics in which any of the materials isdispersed are known.

This embodiment can be combined with any other embodiment asappropriate.

Embodiment 6

In this example, other structure examples of the semiconductor device 10are described.

A structure example of the pixel 21 is shown in FIG. 15A. In the pixel21 in FIG. 15A, an element 900 including a selenium-based semiconductoris used as the photoelectric conversion element 101 shown in FIG. 2 andthe like.

The element including the selenium-based semiconductor is an elementwhich is capable of conducting photoelectric conversion utilizing aphenomenon called avalanche multiplication, in which a plurality ofelectrons can be taken from one incident photon by application ofvoltage. Therefore, in the pixel 21 including the selenium-basedsemiconductor element, the gain of electrons to the amount of incidentlight can be large; therefore, a highly sensitive sensor can beobtained. In a photoelectric conversion element in which aselenium-based material is used for a photoelectric conversion layer,relatively high voltage (e.g., 10 V or higher) is preferably applied toeasily cause the avalanche phenomenon. In addition, an OS transistorwhich is highly resistant to drain voltage is preferably used as each ofthe transistors 102 to 104.

For the selenium-based semiconductor, a selenium-based semiconductorwith an amorphous structure or a selenium-based semiconductor with acrystalline structure can be used. For example, the selenium-basedsemiconductor with a crystalline structure may be obtained in such amanner that a selenium-based semiconductor with an amorphous structureis deposited and subjected to heat treatment. Note that it is preferablethat the crystal grain diameter of the selenium-based semiconductor witha crystalline structure be smaller than a pixel pitch because variationin characteristics of the pixels is reduced and the image quality of animage to be obtained becomes uniform.

A selenium-based semiconductor with a crystalline structure among theselenium-based semiconductors has a characteristic of having a lightabsorption coefficient in a wide wavelength range. Therefore, theelement using selenium-based semiconductor with a crystalline structurecan be used as an imaging element for a wide wavelength range of light,such as visible light, ultraviolet light, X-rays, and gamma rays, andcan be used as what is called a direct conversion element, which iscapable of directly converting light in a short wavelength range, suchas X-rays and gamma rays, into electric charge.

A structure example of the element 900 is shown in FIG. 15B. The element900 includes a substrate 901, an electrode 902, a photoelectricconversion layer 903, and electrodes 904. The electrode 904 is connectedto the source or the drain of the transistor 102. Here, the element 900includes the plurality of photoelectric conversion layers 903 and theplurality of electrodes 904, and each of the plurality of electrodes 904is connected to the corresponding transistor 102; however, there is noparticular limitation on the number of the photoelectric conversionlayers 903 and that of the electrodes 904, and one or more of thephotoelectric conversion layers 903 and one or more of the electrodes904 may be provided for the transistor 102.

Light is to be incident on the photoelectric conversion layers 903through the substrate 901 and the electrode 902. Therefore, thesubstrate 901 and the electrode 902 preferably have a light-transmittingproperty. As the substrate 901, a glass substrate can be used. As theelectrode 902, indium tin oxide (ITO) can be used.

The photoelectric conversion layer 903 contains selenium. Selenium-basedsemiconductors can be used for the photoelectric conversion layer 903.

The photoelectric conversion layer 903 and the electrode 902 stackedover the photoelectric conversion layer 903 can be used withoutprocessing of their shapes for respective pixels 21. Thus, a step forprocessing their shapes can be omitted, which leads to a reduction inthe manufacturing cost and improvement in the manufacturing yield.

A chalcopyrite-based semiconductor can be used for the selenium-basedsemiconductor, for example. Specifically, CuIn_(1-x)Ga_(x)Se₂ (0≦x≦1,abbreviated to CIGS) can be used. CIGS can be formed by an evaporationmethod, a sputtering method, or the like.

The use of a chalcopyrite-based semiconductor as the selenium-basedsemiconductor can cause avalanche multiplication by application ofseveral volts (approximately 5 V to 20 V). Thus, voltage application tothe photoelectric conversion layer 903 can increase straight-runningproperty of the movement of signal charge generated owing to lightirradiation. Note that when the thickness of the photoelectricconversion layer 903 is smaller than or equal to 1 μm, the applicationvoltage can be made smaller. The use of OS transistors as thetransistors 102 to 104 allows the pixel 21 to function normally evenwhen the several volts is applied.

If the thickness of the photoelectric conversion layer 903 is small,dark current sometimes flows at the time of application of voltage;however, such dark current flow can be prevented by providing a layer(hole-injection barrier layer) for inhibiting the dark current fromflowing in the CIGS that is the above-mentioned chalcopyrite-basedsemiconductor. FIG. 15C shows a structure in which a hole-injectionbarrier layer 905 is added to the structure of FIG. 15B.

An oxide semiconductor such as gallium oxide can be used for thehole-injection barrier layer. The thickness of the hole-injectionbarrier layer is preferably smaller than that of the photoelectricconversion layer 903.

As described above, the use of a selenium-based semiconductor for asensor can provide a high-sensitive sensor. The combination of such asensor with one embodiment of the present invention makes it possible toobtain more accurate imaging data.

This embodiment can be combined with any other embodiment asappropriate.

Embodiment 7

In this embodiment, structures of transistors which can be used in theabove embodiments will be described.

<Structure Example 1 of Transistor>

FIG. 16A shows a structure of a transistor 400 which can be used in theembodiments. The transistor 400 is formed over an insulating layer 401with insulating layers 402 and 403 provided therebetween. Although thetransistor 400 is a top-gate transistor, a bottom-gate transistor may beused.

An inverted staggered transistor or a forward staggered transistor canalso be used as the transistor 400. It is also possible to use adual-gate transistor, in which a semiconductor layer in which a channelis formed is interposed between two gate electrodes. Further, thetransistor is not limited to a transistor having a single-gatestructure; a multi-gate transistor having a plurality of channelformation regions, such as a double-gate transistor may be used.

The transistor 400 can be a planar type, a FIN-type, a Tri-Gate type,and the like.

The transistor 400 includes an electrode 443 that can function as a gateelectrode, an electrode 444 that can function as one of a sourceelectrode and a drain electrode, an electrode 445 that can function asthe other of the source electrode and the drain electrode, an insulatinglayer 411 that can function as a gate insulating layer, and asemiconductor layer 421.

The insulating layer 402 is preferably formed using an insulating filmthat has a function of preventing diffusion of impurities such asoxygen, hydrogen, water, alkali metal, and alkaline earth metal.Examples of the insulating film include silicon oxide, siliconoxynitride, silicon nitride, silicon nitride oxide, gallium oxide,hafnium oxide, yttrium oxide, aluminum oxide, aluminum oxynitride, andthe like. When the insulating film is formed using silicon nitride,gallium oxide, hafnium oxide, yttrium oxide, aluminum oxide, or thelike, diffusion of impurities from the insulating layer 401 side to thesemiconductor layer 421 can be reduced. Note that the insulating layer402 can be formed by a sputtering method, a CVD method, an evaporationmethod, a thermal oxidation method, or the like. The insulating layer402 can be formed to have a single-layer structure or a stacked-layerstructure including any of these materials.

The insulating layer 403 can be formed to have a single-layer structureor a multi-layer structure using an oxide material such as aluminumoxide, magnesium oxide, silicon oxide, silicon oxynitride, galliumoxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide,neodymium oxide, hafnium oxide, or tantalum oxide; a nitride materialsuch as silicon nitride, silicon nitride oxide, aluminum nitride, oraluminum nitride oxide; or the like. The insulating layer 403 can beformed by a sputtering method, a CVD method, a thermal oxidation method,a coating method, a printing method, or the like.

In the case where an oxide semiconductor is used for the semiconductorlayer 421, an insulating layer containing oxygen in excess of thestoichiometric composition is preferably used for the insulating layer402. From the insulating layer containing oxygen at a higher proportionthan oxygen in the stoichiometric composition, part of oxygen isreleased by heating. The insulating layer containing oxygen at a higherproportion than oxygen in the stoichiometric composition is aninsulating layer of which the amount of released oxygen converted intooxygen atoms is greater than or equal to 1.0×10¹⁸ atoms/cm³, preferablygreater than or equal to 3.0×10²⁰ atoms/cm³ in TDS analysis. Note thatthe temperature of the layer surface in the TDS analysis is preferablyhigher than or equal to 100° C. and lower than or equal to 700° C., orhigher than or equal to 100° C. and lower than or equal to 500° C.

The insulating layer containing oxygen at a higher proportion than thestoichiometric composition can be formed by treatment for adding oxygento the insulating layer. The treatment for adding oxygen can beperformed by heat treatment under an oxygen atmosphere or performed withan ion implantation apparatus, an ion doping apparatus, or a plasmatreatment apparatus. As a gas for adding oxygen, an oxygen gas of ¹⁶O₂,¹⁸O₂, or the like, a nitrous oxide gas, an ozone gas, or the like can beused. In this specification, the treatment for adding oxygen is alsoreferred to as “oxygen doping treatment”.

The semiconductor layer 421 can be formed using a single crystalsemiconductor, a polycrystalline semiconductor, a microcrystallinesemiconductor, a nanocrystal semiconductor, a semi-amorphoussemiconductor, an amorphous semiconductor, or the like. For example,amorphous silicon or microcrystalline germanium can be used.Alternatively, a compound semiconductor such as silicon carbide, galliumarsenide, an oxide semiconductor, or a nitride semiconductor, an organicsemiconductor, or the like can be used.

In this embodiment, an example in which an oxide semiconductor is usedfor the semiconductor layer 421 is described. Furthermore, in thisembodiment, a case where the semiconductor layer 421 is a stacked layerincluding a semiconductor layer 421 a, a semiconductor layer 421 b, andthe semiconductor layer 421 c is described.

Each of the semiconductor layer 421 a, the semiconductor layer 421 b,and the semiconductor layer 421 c is formed using a material containingeither In or Ga or both of them. Typical examples are an In—Ga oxide (anoxide containing In and Ga), an In—Zn oxide (an oxide containing In andZn), and an In-M-Zn oxide (an oxide containing In, an element M, and Zn:the element M is one or more kinds of metal elements selected from Al,Ti, Ga, Y, Zr, La, Ce, Nd, and Hf whose strength of bonding with oxygenis higher than that of In).

The semiconductor layer 421 a and the semiconductor layer 421 c arepreferably formed using a material containing one or more kinds of metalelements contained in the semiconductor layer 421 b. With the use ofsuch a material, interface states at interfaces between thesemiconductor layer 421 a and the semiconductor layer 421 b and betweenthe semiconductor layer 421 c and the semiconductor layer 421 b are lesslikely to be generated. Accordingly, carriers are not likely to bescattered or captured at the interfaces, which results in an improvementin field-effect mobility of the transistor. Further, threshold-voltagevariation of the transistor can be reduced. Thus, a semiconductor devicehaving favorable electrical characteristics can be obtained.

Each of the thicknesses of the semiconductor layer 421 a and thesemiconductor layer 421 c is greater than or equal to 3 nm and less thanor equal to 100 nm, preferably greater than or equal to 3 nm and lessthan or equal to 50 nm. The thickness of the semiconductor layer 421 bis greater than or equal to 3 nm and less than or equal to 200 nm,preferably greater than or equal to 3 nm and less than or equal to 100nm, more preferably greater than or equal to 3 nm and less than or equalto 50 nm.

In the case where the semiconductor layer 421 b is an In-M-Zn oxide andthe semiconductor layer 421 a and the semiconductor layer 421 c are eachan In-M-Zn oxide, the semiconductor layer 421 a and the semiconductorlayer 421 c each have the atomic ratio where In:M:Zn=x₁:y₁:z₁, and thesemiconductor layer 421 b has an atomic ratio where In:M:Zn=x₂:y₂:z₂,for example. In that case, the compositions of the semiconductor layer421 a, the semiconductor layer 421 c, and the semiconductor layer 421 bare determined so that y₁/x₁ is large than y₂/x₂. It is preferable thatthe compositions of the semiconductor layer 421 a, the semiconductorlayer 421 c, and the semiconductor layer 421 b are determined so thaty₁/x₁ is 1.5 times or more as large as y₂/x₂. It is further preferablethat the compositions of the semiconductor layer 421 a, thesemiconductor layer 421 c, and the semiconductor layer 421 b aredetermined so that y₁/x₁ is twice or more as large as y₂/x₂. It is stillfurther preferable that the compositions of the semiconductor layer 421a, the semiconductor layer 421 c, and the semiconductor layer 421 b aredetermined so that y₁/x₁ is three times or more as large as y₂/x₂. Atthis time, y₁ is preferably greater than or equal to x₁ in thesemiconductor layer 421 b, in which case stable electricalcharacteristics of a transistor can be achieved. However, when y₁ isthree times or more as large as x₁, the field-effect mobility of thetransistor is reduced; accordingly, y₁ is preferably smaller than threetimes x₁. When the semiconductor layer 421 a and the semiconductor layer421 c have the above compositions, the semiconductor layer 421 a and thesemiconductor layer 421 c can each be a layer in which oxygen vacanciesare less likely to be generated than in the semiconductor layer 421 b.

In the case where the semiconductor layer 421 a and the semiconductorlayer 421 c are each an In-M-Zn oxide, the content percentages of In andan element M, not taking Zn and O into consideration, are preferably asfollows: the content percentage of In is lower than 50 atomic % and thepercentage of M is higher than or equal to 50 atomic %. The contentpercentages of In and M are more preferably as follows: the contentpercentage of In is lower than 25 atomic % and the content percentage ofM is higher than or equal to 75 atomic %. In the case where thesemiconductor layer 421 b is an In-M-Zn oxide, the content percentagesof In and element M, not taking Zn and O into consideration, arepreferably as follows: the content percentage of In is higher than orequal to 25 atomic % and the content percentage of M is lower than 75atomic %. The content percentages In and element M are more preferablyas follows: the content percentage of In is higher than or equal to 34atomic % and the content percentage of M is lower than 66 atomic %.

For example, an In—Ga—Zn oxide which is formed using a target having anatomic ratio of In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1:6:4, or 1:9:6 or anIn—Ga oxide which is formed using a target having an atomic ratio ofIn:Ga=1:9 can be used for each of the semiconductor layer 421 a and thesemiconductor layer 421 c containing In or Ga. Furthermore, an In—Ga—Znoxide which is formed using a target having an atomic ratio ofIn:Ga:Zn=3:1:2, 1:1:1, 5:5:6, or 4:2:4.1 can be used for thesemiconductor layer 421 b. Note that the atomic ratio of each of thesemiconductor layer 421 a, the semiconductor layer 421 b, and thesemiconductor layer 421 c may vary within a range of ±20% of any of theabove-described atomic ratios as an error.

In order to give stable electrical characteristics to the transistorincluding the semiconductor layer 421 b, it is preferable thatimpurities and oxygen vacancies in the semiconductor layer 421 b bereduced to obtained a highly purified semiconductor layer; accordingly,the semiconductor layer 421 b can be regarded as an intrinsic orsubstantially intrinsic semiconductor layer. Furthermore, it ispreferable that at least the channel formation region of thesemiconductor layer 421 b be a semiconductor layer that can be regardedas an intrinsic or substantially intrinsic semiconductor layer.

Note that the substantially intrinsic semiconductor layer refers to anoxide semiconductor layer in which the carrier density is lower than1×10¹⁷/cm³, lower than 1×10¹⁵/cm³, or lower than 1×10¹³/cm³.

The function and effect of the semiconductor layer 421 that is a stackedlayer including the semiconductor layer 421 a, the semiconductor layer421 b, and the semiconductor layer 421 c will be described with anenergy band structure diagram shown in FIG. 16B. FIG. 16B is the energyband structure diagram showing a portion along dashed-dotted line A1-A2in FIG. 16A. Thus, FIG. 16B illustrates the energy band structure of achannel formation region of the transistor 400.

In FIG. 16B, Ec403, Ec421 a, Ec421 b, Ec421 c, and Ec411 are theenergies of bottoms of the conduction band in the insulating layer 403,the semiconductor layer 421 a, the semiconductor layer 421 b, thesemiconductor layer 421 c, and the insulating layer 411, respectively.

Here, a difference in energy between the vacuum level and the bottom ofthe conduction band (the difference is also referred to as “electronaffinity”) corresponds to a value obtained by subtracting an energy gapfrom a difference in energy between the vacuum level and the top of thevalence band (the difference is also referred to as an ionizationpotential). Note that the energy gap can be measured using aspectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVONS.A.S.). The energy difference between the vacuum level and the top ofthe valence band can be measured using an ultraviolet photoelectronspectroscopy (UPS) device (VersaProbe manufactured by ULVAC-PHI, Inc.).

Note that an In—Ga—Zn oxide which is formed using a target having anatomic ratio of In:Ga:Zn=1:3:2 has an energy gap of approximately 3.5 eVand an electron affinity of approximately 4.5 eV. An In—Ga—Zn oxidewhich is formed using a target having an atomic ratio of In:Ga:Zn=1:3:4has an energy gap of approximately 3.4 eV and an electron affinity ofapproximately 4.5 eV. An In—Ga—Zn oxide which is formed using a targethaving an atomic ratio of In:Ga:Zn=1:3:6 has an energy gap ofapproximately 3.3 eV and an electron affinity of approximately 4.5 eV.An In—Ga—Zn oxide which is formed using a target having an atomic ratioof In:Ga:Zn=1:6:2 has an energy gap of approximately 3.9 eV and anelectron affinity of approximately 4.3 eV. An In—Ga—Zn oxide which isformed using a target having an atomic ratio of In:Ga:Zn=1:6:8 has anenergy gap of approximately 3.5 eV and an electron affinity ofapproximately 4.4 eV. An In—Ga—Zn oxide which is formed using a targethaving an atomic ratio of In:Ga:Zn=1:6:10 has an energy gap ofapproximately 3.5 eV and an electron affinity of approximately 4.5 eV.An In—Ga—Zn oxide which is formed using a target having an atomic ratioof In:Ga:Zn=1:1:1 has an energy gap of approximately 3.2 eV and anelectron affinity of approximately 4.7 eV. An In—Ga—Zn oxide which isformed using a target having an atomic ratio of In:Ga:Zn=3:1:2 has anenergy gap of approximately 2.8 eV and an electron affinity ofapproximately 5.0 eV.

Since the insulating layer 403 and the insulating layer 411 areinsulators, Ec403 and Ec411 are closer to the vacuum level (have asmaller electron affinity) than Ec421 a, Ec421 b, and Ec421 c.

Further, Ec421 a is closer to the vacuum level than Ec421 b.Specifically, Ec421 a is preferably located closer to the vacuum levelthan Ec421 b by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4eV or less.

Further, Ec421 c is closer to the vacuum level than Ec421 b.Specifically, Ec421 c is preferably located closer to the vacuum levelthan Ec421 b by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4eV or less.

In the vicinity of an interface between the semiconductor layer 421 aand the semiconductor layer 421 b and the vicinity of an interfacebetween the semiconductor layer 421 b and the semiconductor layer 421 c,mixed regions are formed; thus, the energy of the bottom of theconduction band continuously changes. In other words, no state or fewstates exist at these interfaces.

Accordingly, electrons transfer mainly through the semiconductor layer421 b in the stacked-layer structure having the above energy bandstructure. Therefore, even when an interface state exists at aninterface between the semiconductor layer 421 a and the insulating layer401 or an interface between the semiconductor layer 421 c and theinsulating layer 411, the interface state hardly influences the transferof the electrons. In addition, the interface state does not exist orhardly exists at the interface between the semiconductor layer 421 a andthe semiconductor layer 421 b and at the interface between thesemiconductor layer 421 c and the semiconductor layer 421 b; thus,transfer of electrons are not prohibited in the region. Accordingly,high field-effect mobility can be obtained in the transistor 400 havingthe above stacked-layer structure of the oxide semiconductor layers.

Note that although trap states 490 due to impurities or defects might beformed in the vicinity of the interface between the semiconductor layer421 a and the insulating layer 403 and in the vicinity of the interfacebetween the semiconductor layer 421 c and the insulating layer 411 asshown in FIG. 16B, the semiconductor layer 421 b can be separated fromthe trap states owing to the existence of the semiconductor layer 421 aand the semiconductor layer 421 c.

In particular, in the transistor 400 described in this embodiment, anupper surface and a side surface of the semiconductor layer 421 b are incontact with the semiconductor layer 421 c, and a bottom surface of thesemiconductor layer 421 b is in contact with the semiconductor layer 421a. In this manner, the semiconductor layer 421 b is surrounded by thesemiconductor layer 421 a and the semiconductor layer 421 c, whereby theinfluence of the trap state can be further reduced.

However, in the case where an energy difference between Ec421 a or Ec421c and Ec421 b is small, electrons in the semiconductor layer 421 b mightreach the trap states by passing over the energy gap. The electrons aretrapped by the trap states, which generates a negative fixed charge atthe interface with the insulating layer, causing the threshold voltageof the transistor to be shifted in the positive direction.

Therefore, each of the energy differences between Ec421 a and Ec421 band between Ec421 c and Ec421 b is preferably set to be larger than orequal to 0.1 eV, more preferably larger than or equal to 0.15 eV, inwhich case a change in the threshold voltage of the transistor can bereduced and the transistor can have favorable electricalcharacteristics.

Each of the band gaps of the semiconductor layer 421 a and thesemiconductor layer 421 c is preferably larger than that of thesemiconductor layer 421 b.

With one embodiment of the present invention, a transistor with a smallvariation in electrical characteristics can be provided. Accordingly, asemiconductor device with a small variation in electricalcharacteristics can be provided. With one embodiment of the presentinvention, a transistor with high reliability can be provided.Accordingly, a semiconductor device with high reliability can beprovided.

An oxide semiconductor has a band gap of 2 eV or more; therefore, atransistor including an oxide semiconductor in a semiconductor layer inwhich a channel is formed has an extremely small off-state current.Specifically, the off-state current per micrometer of channel width atroom temperature can be lower than 1×10⁻²⁰ A, preferably lower than1×10⁻²² A, more preferably lower than 1×10⁻²⁴ A. That is, the on/offratio of the transistor can be greater than or equal to 20 digits andless than or equal to 150 digits.

With one embodiment of the present invention, a transistor with smallpower consumption can be provided. Accordingly, a semiconductor deviceor an imaging device with low power consumption can be provided. Oneembodiment of the present invention can provide an imaging device or asemiconductor device with high light sensitivity. One embodiment of thepresent invention can also provide an imaging device or a semiconductordevice with a wide dynamic range.

Since an oxide semiconductor has a wide bandgap, a semiconductor deviceincluding an oxide semiconductor can be used in a wide range of ambienttemperature. Accordingly, an imaging device or a semiconductor device ofone embodiment of the present invention has a wide temperature range.

Note that the above-described three-layer structure is just an example.A two-layer structure without the semiconductor layer 421 a or 421 c maybe employed.

As an example of an oxide semiconductor that can be used for thesemiconductor layer 421 a, the semiconductor layer 421 b, and thesemiconductor layer 421 c, an oxide containing indium can be given. Anoxide can have a high carrier mobility (electron mobility) by containingindium, for example. An oxide semiconductor preferably contains anelement M. The element M is preferably aluminum, gallium, yttrium, tin,or the like. Other elements which can be used as the element M areboron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium,molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten,magnesium, and the like. Note that two or more of the above elements maybe used in combination as the element M. The element M is an elementhaving a high bonding energy with oxygen, for example. The element M isan element that can increase the energy gap of the oxide, for example.Further, the oxide semiconductor preferably contains zinc. When theoxide contains zinc, the oxide is easily to be crystallized, forexample.

Note that the oxide semiconductor is not limited to the oxide containingindium. The oxide semiconductor may be, for example, zinc tin oxide,gallium tin oxide, or gallium oxide.

For the oxide semiconductor, an oxide with a wide energy gap is used.For example, the energy gap of the oxide semiconductor is greater thanor equal to 2.5 eV and less than or equal to 4.2 eV, preferably greaterthan or equal to 2.8 eV and less than or equal to 3.8 eV, morepreferably greater than or equal to 3 eV and less than or equal to 3.5eV.

Influence of impurities in the oxide semiconductor will be describedbelow. In order to obtain stable electrical characteristics of atransistor, it is effective to reduce the concentration of impurities inthe oxide semiconductor to have lower carrier density so that the oxidesemiconductor is highly purified. The carrier density of the oxidesemiconductor is set to be lower than 1×10¹⁷/cm³, lower than 1×10¹⁵/cm³,or lower than 1×10¹³/cm³. In particular, the carrier density of theoxide semiconductor is lower than 8×10¹¹/cm³, preferably lower than1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and is higher thanor equal to 1×10⁻⁹/cm³. In order to reduce the concentration ofimpurities in the oxide semiconductor, the concentration of impuritiesin a film which is adjacent to the oxide semiconductor is preferablyreduced.

For example, silicon in the oxide semiconductor might serve as a carriertrap or a carrier generation source. The silicon concentration in theoxide semiconductor measured by secondary ion mass spectrometry (SIMS)is lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³,more preferably lower than 2×10¹⁸ atoms/cm³.

Furthermore, when hydrogen is contained in the oxide semiconductor, thecarrier density is increased in some cases. Thus, the concentration ofhydrogen in the oxide semiconductor, which is measured by SIMS, can beset to lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than orequal to 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 1×10¹⁹atoms/cm³, still more preferably lower than or equal to 5×10¹⁸atoms/cm³. When nitrogen is contained in the oxide semiconductor, thecarrier density is increased in some cases. The concentration ofnitrogen in the oxide semiconductor measured by SIMS is set to be lowerthan 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸atoms/cm³, more preferably lower than or equal to 1×10¹⁸ atoms/cm³,still more preferably lower than or equal to 5×10¹⁷ atoms/cm³.

In order to reduce the hydrogen concentration in the oxidesemiconductor, the hydrogen concentrations in the insulating layer 403and the insulating layer 411 that are in contact with the semiconductorlayer 421 are preferably reduced. The hydrogen concentration in theinsulating layer 403 and the insulating layer 411 measured by SIMS islower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equalto 5×10¹⁹ atoms/cm³, more preferably lower than or equal to 1×10¹⁹atoms/cm³, still more preferably lower than or equal to 5×10¹⁸atoms/cm³. In order to reduce the nitrogen concentration in the oxidesemiconductor, the nitrogen concentrations in the insulating layer 403and the insulating layer 411 are preferably reduced. The nitrogenconcentration in the insulating layer 403 and the insulating layer 411measured by SIMS is lower than 5×10¹⁹ atoms/cm³, preferably lower thanor equal to 5×10¹⁸ atoms/cm³, more preferably lower than or equal to1×10¹⁸ atoms/cm³, still more preferably lower than or equal to 5×10¹⁷atoms/cm³.

In this embodiment, first, the semiconductor layer 421 a is formed overthe insulating layer 403, and the semiconductor layer 421 b is formedover the semiconductor layer 421 a.

A sputtering method is preferably used for formation of the oxidesemiconductor layers. As a sputtering method, an RF sputtering method, aDC sputtering method, an AC sputtering method, or the like can be used.A DC sputtering method or an AC sputtering method can achieve uniformdeposition as compared to an RF sputtering method.

In this embodiment, as the semiconductor layer 421 a, 20-nm-thickIn—Ga—Zn oxide is deposited by a sputtering method using an In—Ga—Znoxide target (In:Ga:Zn=1:3:2). Note that the constituent elements andcompositions applicable to the semiconductor layer 421 a are not limitedthereto.

The oxygen doping treatment may be performed after the formation of thesemiconductor layer 421 a.

Next, the semiconductor layer 421 b is formed over the semiconductorlayer 421 a. In this embodiment, as the semiconductor layer 421 b,30-nm-thick In—Ga—Zn oxide is deposited by a sputtering method using anIn—Ga—Zn oxide target (In:Ga:Zn=1:1:1). Note that the constituentelements and compositions applicable to the semiconductor layer 421 bare not limited thereto.

The oxygen doping treatment may be performed after the formation of thesemiconductor layer 421 b.

Next, heat treatment may be performed to further reduce the impuritiessuch as moisture or hydrogen contained in the semiconductor layer 421 aand the semiconductor layer 421 b, so that the semiconductor layer 421 aand the semiconductor layer 421 b are highly purified.

For example, the semiconductor layer 421 a and the semiconductor layer421 b are subjected to heat treatment in a reduced-pressure atmosphere,an inert gas atmosphere of nitrogen, a rare gas, or the like, anoxidation atmosphere, or an ultra dry air atmosphere (the moistureamount is 20 ppm (−55° C. by conversion into a dew point) or less,preferably 1 ppm or less, more preferably 10 ppb or less, in the casewhere the measurement is performed by a dew point meter in a cavity ringdown laser spectroscopy (CRDS) system). Note that the oxidationatmosphere refers to an atmosphere including an oxidation gas such asoxygen, ozone, or nitrogen oxide at 10 ppm or higher. The inert gasatmosphere refers to an atmosphere including the oxidation gas at lowerthan 10 ppm and is filled with nitrogen or a rare gas.

By heat treatment, oxygen included in the insulating layer 403 can bediffused into the semiconductor layer 421 a and the semiconductor layer421 b, concurrently with the release of impurities, so that oxygenvacancies in the semiconductor layer 421 a and the semiconductor layer421 b can be reduced. Note that the heat treatment may be performed insuch a manner that heat treatment is performed in an inert gasatmosphere, and then another heat treatment is performed in anatmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or10% or more. The heat treatment may be performed at any time after thesemiconductor layer 421 b is formed. For example, the heat treatment maybe performed after the semiconductor layer 421 b is selectively etched.

The heat treatment can be performed at a temperature higher than orequal to 250° C. and lower than or equal to 650° C., preferably higherthan or equal to 300° C. and lower than or equal to 500° C. Thetreatment time is shorter than or equal to 24 hours.

An electric furnace, an RTA apparatus, or the like can be used for theheat treatment. The use of an RTA apparatus allows the heat treatment ata temperature of higher than or equal to the strain point of thesubstrate if the heating time is short. Therefore, the heat treatmenttime can be shortened.

Next, a resist mask is formed over the semiconductor layer 421 b, andwith use of the resist mask, part of the semiconductor layer 421 a andpart of the semiconductor layer 421 b are etched selectively. At thistime, the insulating layer 403 might be partly etched, thereby having aprojection.

Either of a dry etching method or a wet etching method may be used foretching of the semiconductor layer 421 a and the semiconductor layer 421b, or both of them may be used. After the etching, the resist mask isremoved.

The transistor 400 includes an electrode 444 and an electrode 445 overand partly in contact with the semiconductor layer 421 b. The electrodes444 and 445 can be formed with a single-layer structure or astacked-layer structure using any of metals such as aluminum, titanium,chromium, nickel, copper, yttrium, zirconium, molybdenum, manganese,silver, tantalum, and tungsten, or an alloy containing any of thesemetals as its main component. For example, a single-layer structure of acopper film containing manganese; a two-layer structure in which analuminum film is stacked over a titanium film; a two-layer structure inwhich an aluminum film is stacked over a tungsten film; a two-layerstructure in which a copper film is stacked over acopper-magnesium-aluminum alloy film; a two-layer structure in which acopper film is stacked over a titanium film; a two-layer structure inwhich a copper film is stacked over a tungsten film; a three-layerstructure in which a titanium film or a titanium nitride film, analuminum film or a copper film, and a titanium film or a titaniumnitride film are stacked in this order; a three-layer structure in whicha molybdenum film or a molybdenum nitride film, an aluminum film or acopper film, and a molybdenum film or a molybdenum nitride film arestacked in this order; a three-layer structure in which a tungsten film,a copper film, and a tungsten film are stacked in this order; and thelike can be given. Alternatively, an alloy film or a nitride film inwhich aluminum and one or more elements selected from titanium,tantalum, tungsten, molybdenum, chromium, neodymium, and scandium arecombined may be used.

In addition, the transistor 400 includes the semiconductor layer 421 cover the semiconductor layer 421 b, the electrode 444, and the electrode445. The semiconductor layer 421 c is partly in contact with each of thesemiconductor layer 421 b, the electrode 444, and the electrode 445.

In this embodiment, the semiconductor layer 421 c is formed by asputtering method using an In—Ga—Zn oxide target (In:Ga:Zn=1:3:2). Notethat the constituent elements and compositions applicable to thesemiconductor layer 421 c are not limited thereto. For example, oxidegallium may be used for the semiconductor layer 421 c. Furthermore,oxygen doping treatment may be performed on the semiconductor layer 421c.

Furthermore, in the transistor 400, the insulating layer 411 is providedover the semiconductor layer 421 c. The insulating layer 411 canfunction as a gate insulating layer. The insulating layer 411 can beformed using a material and a method similar to those of the insulatinglayer 403. The oxygen doping treatment may be performed on theinsulating layer 411.

After the semiconductor layer 421 c and the insulating layer 411 areformed, a mask is formed over the insulating layer 411, and parts of thesemiconductor layer 421 c and the insulating layer 411 are selectivelyetched, so that the semiconductor layer 421 c and the insulating layer411 may be formed into island shapes.

Moreover in the transistor 400, the electrode 443 is provided over theinsulating layer 411. The electrode 443 (including another electrode orwiring that is formed in the same layer as this electrode) can be formedusing a material and a method similar to those of the electrodes 444 and445.

In this embodiment, an example in which the electrode 443 has astacked-layer structure including an electrode 443 a and an electrode443 b is shown. For example, the electrode 443 a is formed usingtantalum nitride, and the electrode 443 b is formed using copper. Theelectrode 443 a functions as a barrier layer to prevent copperdiffusion. Thus, a semiconductor device with high reliability can beobtained.

Moreover, the transistor 400 includes an insulating layer 412 coveringthe electrode 443. The insulating layer 412 can be formed using amaterial and a method similar to those of the insulating layer 403. Theinsulating layer 412 may be subjected to oxygen doping treatment.Furthermore, a surface of the insulating layer 412 may be subjected toCMP treatment.

In addition, an insulating layer 413 is over the insulating layer 412.The insulating layer 413 can be formed using a material and a methodthat are similar to those of the insulating layer 403. A surface of theinsulating layer 413 may be subjected to CMP treatment. By the CMPtreatment, unevenness of the surface can be reduced, and coverage withan insulating layer or a conductive layer formed later can be increased.

<Structure Example 2 of Transistor>

Next, a structure example of a transistor that can be used as thetransistor 400 will be described with reference to FIGS. 17A1, 17A2,17B1, and 17B2, FIGS. 18A1, 18A2, 18A3, 18B1, and 18B2, FIGS. 19A, 19B,and 19C, FIGS. 20A, 20B, and 20C, and FIGS. 21A, 21B, and 21C.

[Bottom-Gate Transistor]

A transistor 510 shown in FIG. 17A1 as an example is achannel-protective transistor that is a type of bottom-gate transistor.The transistor 510 includes an electrode 446 that can function as a gateelectrode over an insulating layer 403. The transistor 510 includes asemiconductor layer 421 over the electrode 446 with an insulating layer411 positioned therebetween. The electrode 446 can be formed using amaterial and a method similar to those of the electrodes 444 and 445.

The transistor 510 includes an insulating layer 450 that can function asa channel protective layer over a channel formation region in thesemiconductor layer 421. The insulating layer 450 can be formed using amaterial and a method that are similar to those of the insulating layer411. Part of an electrode 444 and part of an electrode 445 are formedover the insulating layer 450.

With the insulating layer 450 provided over the channel formationregion, the semiconductor layer 421 can be prevented from being exposedat the time of forming the electrode 444 and the electrode 445. Thus,the semiconductor layer 421 can be prevented from being reduced inthickness at the time of forming the electrode 444 and the electrode445. According to one embodiment of the present invention, a transistorwith favorable electrical characteristics can be provided.

A transistor 511 illustrated in FIG. 17A2 is different from thetransistor 510 in that an electrode 451 that can function as a back gateelectrode is provided over an insulating layer 412. The electrode 451can be formed using a material and a method that are similar to those ofthe electrodes 444 and 445.

In general, the back gate electrode is formed using a conductive layerand positioned so that the channel formation region of the semiconductorlayer is positioned between the gate electrode and the back gateelectrode. Thus, the back gate electrode can function in a mannersimilar to that of the gate electrode. The potential of the back gateelectrode may be the same as that of the gate electrode or may be a GNDpotential or a predetermined potential. By changing the potential of theback gate electrode independently of the potential of the gateelectrode, the threshold voltage of the transistor can be changed.

The electrodes 446 and 451 can both function as gate electrodes. Thus,the insulating layers 411, 450, and 412 can all function as gateinsulating layers.

In the case where one of the electrode 446 and the electrode 451 issimply referred to as a “gate electrode”, the other can be referred toas a “back gate electrode”. For example, in the transistor 511, in thecase where the electrode 451 is referred to as a “gate electrode”, theelectrode 446 may be referred to as a “back gate electrode”. In the casewhere the electrode 451 is used as a “gate electrode”, the transistor511 can be considered as a kind of top-gate transistor. Furthermore, oneof the electrode 446 and the electrode 451 may be referred to as a“first gate electrode”, and the other may be referred to as a “secondgate electrode”.

By providing the electrode 446 and the electrode 451 with thesemiconductor layer 421 positioned therebetween and setting thepotentials of the electrode 446 and the electrode 451 to be the same, aregion of the semiconductor layer 421 through which carriers flow isenlarged in the film thickness direction; thus, the number oftransferred carriers is increased. As a result, the on-state current andthe field-effect mobility of the transistor 511 are increased.

Therefore, the transistor 511 has large on-state current for the areaoccupied thereby. That is, the area occupied by the transistor 511 canbe small for required on-state current. With one embodiment of thepresent invention, the area occupied by a transistor can be reduced.Therefore, with one embodiment of the present invention, a semiconductordevice having a high degree of integration can be provided.

Furthermore, the gate electrode and the back gate electrode are formedusing conductive layers and thus each have a function of preventing anelectric field generated outside the transistor from influencing thesemiconductor layer in which the channel is formed (in particular, anelectric field blocking function against static electricity and thelike). When the back gate electrode is formed larger than thesemiconductor layer such that the semiconductor layer is covered withthe back gate electrode, the electric field blocking function can beenhanced.

Since the electrode 446 and the electrode 451 each have a function ofblocking an electric field generated outside, charges of chargedparticles and the like generated on the insulating layer 403 side orabove the electrode 451 do not influence the channel formation region inthe semiconductor layer 421. Therefore, degradation in a stress test(e.g., a negative gate bias temperature (−GBT) stress test in whichnegative charges are applied to a gate) can be reduced, and changes inthe rising voltages of on-state current at different drain voltages canbe reduced. Note that this effect can be obtained when the electrodes446 and 451 have the same potential or different potentials.

The BT stress test is one kind of accelerated test and can evaluate, ina short time, a change caused by long-term use (i.e., a change overtime) in characteristics of transistors. In particular, the amount ofchange in threshold voltage of the transistor between before and afterthe BT stress test is an important indicator when examining thereliability of the transistor. If the amount of change in the thresholdvoltage between before and after the BT stress test is small, thetransistor has higher reliability.

By providing the electrode 446 and the electrode 451 and setting thepotentials of the electrode 446 and the electrode 451 to be the same,the change in threshold voltage is reduced. Accordingly, variation inelectrical characteristics among a plurality of transistors is alsoreduced.

The transistor including the back gate electrode has a smaller change inthreshold voltage by a positive GBT stress test in which positiveelectric charge is applied to a gate than a transistor including no backgate electrode.

In the case where light is incident on the back gate electrode side,when the back gate electrode is formed using a light-blocking conductivefilm, light can be prevented from entering the semiconductor layer fromthe back gate electrode side. Therefore, photodegradation of thesemiconductor layer can be prevented and deterioration in electricalcharacteristics of the transistor, such as a shift of the thresholdvoltage, can be prevented.

With one embodiment of the present invention, a transistor with highreliability can be provided. Moreover, a semiconductor device with highreliability can be provided.

A transistor 520 shown in FIG. 17B1 as an example is achannel-protective transistor that is a type of bottom-gate transistor.The transistor 520 has substantially the same structure as thetransistor 510 but is different from the transistor 510 in that theinsulating layer 450 covers the semiconductor layer 421. Furthermore,the semiconductor layer 421 is electrically connected to the electrode444 in the opening which is formed by selectively removing part of theinsulating layer 450 overlapping the semiconductor layer 421.Furthermore, the semiconductor layer 421 is electrically connected tothe electrode 445 in the opening which is formed by selectively removingpart of the insulating layer 450 overlapping the semiconductor layer421. A region of the insulating layer 450 which overlaps the channelformation region can function as a channel protective layer.

A transistor 521 illustrated in FIG. 17B2 is different from thetransistor 520 in that the electrode 451 that can function as a backgate electrode is provided over the insulating layer 412. Each of theelectrodes 446 and 451 can function as a gate electrode. Accordingly,each of the insulating layers 411, 450, and 412 can function as a gateinsulating layer.

The distance between the electrode 444 and the electrode 446 and thedistance between the electrode 445 and the electrode 446 in thetransistors 520 and 521 are longer than those in the transistors 510 and511. Thus, the parasitic capacitance generated between the electrode 444and the electrode 446 can be reduced. The parasitic capacitancegenerated between the electrode 445 and the electrode 446 can also bereduced. According to one embodiment of the present invention, atransistor with favorable electrical characteristics can be provided.

[Top-Gate Transistor]

A transistor 530 shown in FIG. 18A1 as an example is a type of top-gatetransistor. The transistor 530 includes the semiconductor layer 421 overthe insulating layer 403; the electrode 444 in contact with part of thesemiconductor layer 421 and the electrode 445 in contact with part ofthe semiconductor layer 421, over the semiconductor layer 421 and theinsulating layer 403; the insulating layer 411 over the semiconductorlayer 421, the electrode 444, and the electrode 445; and the electrode446 over the insulating layer 411.

Since, in the transistor 530, the electrode 446 overlaps with neitherthe electrode 444 nor the electrode 445, the parasitic capacitancegenerated between the electrode 446 and the electrode 444 and theparasitic capacitance generated between the electrode 446 and theelectrode 445 can be reduced. After the formation of the electrode 446,an impurity element 455 is introduced into the semiconductor layer 421using the electrode 446 as a mask, so that an impurity region can beformed in the semiconductor layer 421 in a self-aligned manner (see FIG.18A3). According to one embodiment of the present invention, atransistor with favorable electrical characteristics can be provided.

The introduction of the impurity element 455 can be performed with anion implantation apparatus, an ion doping apparatus, or a plasmatreatment apparatus. As the ion doping apparatus, an ion dopingapparatus with a mass separation function may be used.

As the impurity element 455, for example, at least one kind of elementof Group 13 elements and Group 15 elements can be used. In the casewhere an oxide semiconductor is used for the semiconductor layer 421, itis possible to use at least one kind of element of a rare gas, hydrogen,and nitrogen as the impurity element 455.

A transistor 531 illustrated in FIG. 18A2 is different from thetransistor 530 in that the electrode 451 and an insulating layer 417 areprovided. The transistor 531 includes the electrode 451 formed over theinsulating layer 403 and the insulating layer 417 formed over theelectrode 451. As described above, the electrode 451 can function as aback gate electrode. Thus, the insulating layer 417 can function as agate insulating layer. The insulating layer 417 can be formed using amaterial and a method that are similar to those of the insulating layer411.

The transistor 531 as well as the transistor 511 has large on-statecurrent for the area occupied thereby. That is, the area occupied by thetransistor 531 can be small for required on-state current. With oneembodiment of the present invention, the area occupied by a transistorcan be reduced. Therefore, with one embodiment of the present invention,a semiconductor device having a high degree of integration can beprovided.

A transistor 540 shown in FIG. 18B1 as an example is a type of top-gatetransistor. The transistor 540 is different from the transistor 530 inthat the semiconductor layer 421 is formed after the formation of theelectrode 444 and the electrode 445. A transistor 541 illustrated inFIG. 18B2 is different from the transistor 540 in that the electrode 451and the insulating layer 417 are provided. Thus, in the transistors 540and 541, part of the semiconductor layer 421 is formed over theelectrode 444 and another part of the semiconductor layer 421 is formedover the electrode 445.

The transistor 541 as well as the transistor 511 has large on-statecurrent for the area occupied thereby. That is, the area occupied by thetransistor 541 can be small for required on-state current. With oneembodiment of the present invention, the area occupied by a transistorcan be reduced. Therefore, with one embodiment of the present invention,a semiconductor device having a high degree of integration can beprovided.

Also in the transistors 540 and 541, after the formation of theelectrode 446, the impurity element 455 is introduced into thesemiconductor layer 421 using the electrode 446 as a mask, so that animpurity region can be formed in the semiconductor layer 421 in aself-aligned manner. According to one embodiment of the presentinvention, a transistor with favorable electrical characteristics can beprovided. Furthermore, according to one embodiment of the presentinvention, a semiconductor device having a high degree of integrationcan be provided.

[S-Channel Transistor]

A transistor 550 illustrated in FIGS. 19A to 19C has a structure inwhich a top surface and side surface of the semiconductor layer 421 bare covered with the semiconductor layer 421 a. FIG. 19A is the top viewof the transistor 550. FIG. 19B is a cross-sectional view (in thechannel length direction) taken along dashed-dotted line X1-X2 in FIG.19A. FIG. 19C is a cross-sectional view (in the channel width direction)taken along dashed-dotted line Y1-Y2 in FIG. 19A.

With the semiconductor layer 421 provided on the projection of theinsulating layer 403, the side surface of the semiconductor layer 421 bcan be covered with the electrode 443. Thus, the transistor 550 has astructure in which the semiconductor layer 421 b can be electricallysurrounded by electric field of the electrode 443. In this way, thestructure of a transistor in which the semiconductor layer iselectrically surrounded by the electric field of the conductive film iscalled a surrounded channel (s-channel) structure. A transistor havingan s-channel structure is referred to as an s-channel transistor.

In the transistor with an s-channel structure, a channel is formed inthe whole (bulk) of the semiconductor layer 421 b in some cases. In thes-channel structure, the drain current of the transistor is increased,so that a larger amount of on-state current can be obtained.Furthermore, the entire channel formation region of the semiconductorlayer 421 b can be depleted by the electric field of the electrode 443.Accordingly, off-state current of the transistor with an s-channelstructure can be further reduced.

When the projecting portion of the insulating layer 403 is increased inheight, and the channel width is shortened, the effects of the s-channelstructure to increase the on-state current and reduce the off-statecurrent can be enhanced. Part of the semiconductor layer 421 a exposedin the formation of the semiconductor layer 421 b may be removed. Inthis case, the side surfaces of the semiconductor layer 421 a and thesemiconductor layer 421 b may be aligned to each other.

As in a transistor 551 illustrated in FIGS. 20A to 20C, the electrode451 may be provided below the semiconductor layer 421 with an insulatinglayer interposed therebetween. FIG. 20A is a top view of the transistor551. FIG. 20B is a cross-sectional view taken along the dashed-dottedline X1-X2 in FIG. 20A. FIG. 20C is a cross-sectional view taken alongthe dashed-dotted line Y1-Y2 in FIG. 20A.

As in a transistor 452 illustrated in FIGS. 21A to 21C, a layer 414 maybe provided over the electrode 443. FIG. 21A is a top view of thetransistor 452. FIG. 21B is a cross-sectional view taken along thedashed-dotted line X1-X2 in FIG. 21A. FIG. 21C is a cross-sectional viewtaken along the dashed-dotted line Y1-Y2 in FIG. 21A.

The layer 414 is provided over the insulating layer 413 in FIGS. 21A to21C; however, the layer 414 may be provided over the insulating layer412. When the layer 414 is formed using a material having alight-blocking property, change in characteristics or decrease inreliability of the transistor, which is caused by light irradiation, canbe prevented. When the layer 414 is formed at least larger than thesemiconductor layer 421 b such that the semiconductor layer 421 b iscovered with the layer 414, the above effects can be improved. The layer414 can be formed using an organic material, an inorganic material, or ametal material. In the case where the layer 414 is formed using aconductive material, voltage can be supplied to the layer 414 or thelayer 414 may be set to an electrically-floating state.

<Structure of Oxide Semiconductor>

A structure of an oxide semiconductor is described below.

In this specification, the term “parallel” indicates that the angleformed between two straight lines is greater than or equal to −10° andless than or equal to 10°, and accordingly also includes the case wherethe angle is greater than or equal to −5° and less than or equal to 5°.A term “substantially parallel” indicates that the angle formed betweentwo straight lines is greater than or equal to −30° and less than orequal to 30°. In addition, the term “perpendicular” indicates that theangle formed between two straight lines is greater than or equal to 80°and less than or equal to 100°, and accordingly also includes the casewhere the angle is greater than or equal to 85° and less than or equalto 95°. A term “substantially perpendicular” indicates that the angleformed between two straight lines is greater than or equal to 60° andless than or equal to 120°. In this specification, trigonal andrhombohedral crystal systems are included in a hexagonal crystal system.

An oxide semiconductor film is classified into, for example, anon-single-crystal oxide semiconductor film and a single crystal oxidesemiconductor film. Alternatively, an oxide semiconductor is classifiedinto, for example, a crystalline oxide semiconductor and an amorphousoxide semiconductor.

Examples of a non-single-crystal oxide semiconductor include a c-axisaligned crystalline oxide semiconductor (CAAC-OS), a polycrystallineoxide semiconductor, a microcrystalline oxide semiconductor, and anamorphous oxide semiconductor. In addition, examples of a crystallineoxide semiconductor include a single crystal oxide semiconductor, aCAAC-OS, a polycrystalline oxide semiconductor, and a microcrystallineoxide semiconductor.

[CAAC-OS]

A CAAC-OS film is one of oxide semiconductor films having a plurality ofc-axis aligned crystal parts.

With a transmission electron microscope (TEM), a combined analysis image(also referred to as a high-resolution TEM image) of a bright-fieldimage and a diffraction pattern of the CAAC-OS film is observed.Consequently, a plurality of crystal parts are observed clearly.However, even in the high-resolution TEM image, a boundary between thecrystal parts, that is, a grain boundary is not clearly observed. Thus,in the CAAC-OS film, a reduction in electron mobility due to the grainboundary is less likely to occur.

According to the high-resolution cross-sectional TEM image of theCAAC-OS film observed in a direction substantially parallel to a samplesurface, metal atoms are arranged in a layered manner in the crystalparts. Each metal atom layer has a morphology reflecting a surface overwhich the CAAC-OS film is formed (hereinafter, a surface over which theCAAC-OS film is formed is referred to as a formation surface) or a topsurface of the CAAC-OS film, and is arranged parallel to the formationsurface or the top surface of the CAAC-OS film.

On the other hand, according to the high-resolution planar TEM image ofthe CAAC-OS film observed in a direction substantially perpendicular tothe sample surface, metal atoms are arranged in a triangular orhexagonal configuration in the crystal parts. However, there is noregularity of arrangement of metal atoms between different crystalparts.

A CAAC-OS film is subjected to structural analysis with an X-raydiffraction (XRD) apparatus. For example, when the CAAC-OS filmincluding an InGaZnO₄ crystal is analyzed by an out-of-plane method, apeak will appear when the diffraction angle (2θ) is around 31°. Thispeak is derived from the (009) plane of the InGaZnO₄ crystal, whichindicates that crystals in the CAAC-OS film have c-axis alignment, andthat the c-axes are aligned in a direction substantially perpendicularto the formation surface or the top surface of the CAAC-OS film.

Note that when the CAAC-OS film with an InGaZnO₄ crystal is analyzed byan out-of-plane method, a peak of 2θ may also be observed at around 36°,in addition to the peak of 2θ at around 31°. The peak of 2θ at around36° indicates that a crystal having no c-axis alignment is included inpart of the CAAC-OS film. It is preferable that in the CAAC-OS film, apeak of 2θ appear at around 31° and a peak of 2θ not appear at around36°.

The CAAC-OS film is an oxide semiconductor film having low impurityconcentration. The impurity is an element other than the main componentsof the oxide semiconductor film, such as hydrogen, carbon, silicon, or atransition metal element. In particular, an element that has higherbonding strength to oxygen than a metal element included in the oxidesemiconductor film, such as silicon, disturbs the atomic arrangement ofthe oxide semiconductor film by depriving the oxide semiconductor filmof oxygen and causes a decrease in crystallinity. Further, a heavy metalsuch as iron or nickel, argon, carbon dioxide, or the like has a largeatomic radius (molecular radius), and thus disturbs the atomicarrangement of the oxide semiconductor film and causes a decrease incrystallinity when it is contained in the oxide semiconductor film. Notethat the impurity contained in the oxide semiconductor film might serveas a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film having a low density ofdefect states. In some cases, oxygen vacancies in the oxidesemiconductor film serve as carrier traps or serve as carrier generationsources when hydrogen is captured therein.

The state in which impurity concentration is low and a density of defectstates is low (the number of oxygen vacancies is small) is referred toas a “highly purified intrinsic” or “substantially highly purifiedintrinsic” state. A highly purified intrinsic or substantially highlypurified intrinsic oxide semiconductor film has few carrier generationsources, and thus can have a low carrier density. Thus, a transistorincluding the oxide semiconductor film rarely has negative thresholdvoltage (is rarely normally on). In addition, the highly purifiedintrinsic or substantially highly purified intrinsic oxide semiconductorfilm has few carrier traps. Accordingly, the transistor including theoxide semiconductor film has little variation in electricalcharacteristics and high reliability. Electric charge trapped by thecarrier traps in the oxide semiconductor film takes a long time to bereleased, and might behave like fixed electric charge. Thus, thetransistor which includes the oxide semiconductor film having highimpurity concentration and a high density of defect states has unstableelectrical characteristics in some cases.

With the use of the CAAC-OS film in a transistor, variation in theelectrical characteristics of the transistor due to irradiation withvisible light or ultraviolet light is small.

[Microcrystalline Oxide Semiconductor Film]

A microcrystalline oxide semiconductor film has a region where a crystalpart is observed in a high resolution TEM image and a region where acrystal part is not clearly observed in a high resolution TEM image. Inmost cases, a crystal part in the microcrystalline oxide semiconductorfilm is greater than or equal to 1 nm and less than or equal to 100 nm,or greater than or equal to 1 nm and less than or equal to 10 nm. Amicrocrystal with a size greater than or equal to 1 nm and less than orequal to 10 nm, or a size greater than or equal to 1 nm and less than orequal to 3 nm is specifically referred to as nanocrystal (nc). An oxidesemiconductor film including nanocrystal is referred to as an nc-OS(nanocrystalline oxide semiconductor) film. In a high resolution TEMimage of the nc-OS film, for example, a grain boundary cannot be foundclearly in the nc-OS film in some cases.

In the nc-OS film, a microscopic region (for example, a region with asize greater than or equal to 1 nm and less than or equal to 10 nm, inparticular, a region with a size greater than or equal to 1 nm and lessthan or equal to 3 nm) has a periodic atomic order. Note that there isno regularity of crystal orientation between different crystal parts inthe nc-OS film. Thus, the orientation of the whole film is not observed.Accordingly, in some cases, the nc-OS film cannot be distinguished froman amorphous oxide semiconductor film depending on an analysis method.For example, when the nc-OS film is subjected to structural analysis byan out-of-plane method with an XRD apparatus using an X-ray having adiameter larger than that of a crystal part, a peak which shows acrystal plane does not appear. Further, a diffraction pattern like ahalo pattern appears in a selected-area electron diffraction pattern ofthe nc-OS film that is obtained by using an electron beam having a probediameter (e.g., larger than or equal to 50 nm) larger than the diameterof a crystal part. Meanwhile, spots are shown in a nanobeam electrondiffraction pattern of the nc-OS film obtained by using an electron beamhaving a probe diameter close to, or smaller than the diameter of acrystal part. Further, in a nanobeam electron diffraction pattern of thenc-OS film, regions with high luminance in a circular (ring) pattern areshown in some cases. Also in a nanobeam electron diffraction pattern ofthe nc-OS film, a plurality of spots is shown in a ring-like region insome cases.

The nc-OS film is an oxide semiconductor film that has high regularityas compared to an amorphous oxide semiconductor film. Therefore, thenc-OS film has a lower density of defect states than an amorphous oxidesemiconductor film. However, there is no regularity of crystalorientation between different crystal parts in the nc-OS film; hence,the nc-OS film has a higher density of defect states than the CAAC-OSfilm.

[Amorphous Oxide Semiconductor Film]

An amorphous oxide semiconductor film has disordered atomic arrangementand no crystal part. For example, the amorphous oxide semiconductor filmdoes not have a specific state as in quartz.

In the high-resolution TEM image of the amorphous oxide semiconductorfilm, crystal parts cannot be found.

When the amorphous oxide semiconductor film is subjected to structuralanalysis by an out-of-plane method with an XRD apparatus, a peak whichshows a crystal plane does not appear. A halo pattern is shown in anelectron diffraction pattern of the amorphous oxide semiconductor film.Further, a halo pattern is shown but a spot is not shown in a nanobeamelectron diffraction pattern of the amorphous oxide semiconductor film.

Note that an oxide semiconductor film may have a structure havingphysical properties between the nc-OS film and the amorphous oxidesemiconductor film. The oxide semiconductor film having such a structureis specifically referred to as an amorphous-like oxide semiconductor(a-like OS) film.

In a high-resolution TEM image of the a-like OS film, a void may beseen. Furthermore, in the high-resolution TEM image, there are a regionwhere a crystal part is clearly observed and a region where a crystalpart is not observed. In the a-like OS film, crystallization by a slightamount of electron beam used for TEM observation occurs and growth ofthe crystal part is found sometimes. In contrast, crystallization by aslight amount of electron beam used for TEM observation is less observedin the nc-OS film having good quality.

Note that the crystal part size in the a-like OS film and the nc-OS filmcan be measured using high-resolution TEM images. For example, anInGaZnO₄ crystal has a layered structure in which two Ga—Zn—O layers areincluded between In—O layers. A unit cell of the InGaZnO₄ crystal has astructure in which nine layers of three In—O layers and six Ga—Zn—Olayers are layered in the c-axis direction. Accordingly, the spacingbetween these adjacent layers is equivalent to the lattice spacing onthe (009) plane (also referred to as d value). The value is calculatedto 0.29 nm from crystal structure analysis. Thus, each of the latticefringes in which the spacing therebetween is from 0.28 nm to 0.30 nmcorresponds to the a-b plane of the InGaZnO₄ crystal, when focusing onthe lattice fringes in the high-resolution TEM image.

The density of an oxide semiconductor film might vary depending on itsstructure. For example, if the composition of an oxide semiconductorfilm is determined, the structure of the oxide semiconductor film can beestimated from a comparison between the density of the oxidesemiconductor film and the density of a single crystal oxidesemiconductor having the same composition as the oxide semiconductorfilm. For example, the density of the a-like OS film is higher than orequal to 78.6% and lower than 92.3% of the density of the single crystaloxide semiconductor having the same composition. For example, thedensity of each of the nc-OS film and the CAAC-OS film is higher than orequal to 92.3% and lower than 100% of the density of the single crystaloxide semiconductor having the same composition. Note that it isdifficult to deposit an oxide semiconductor film whose density is lowerthan 78% of the density of the single crystal oxide semiconductor film.

Specific examples of the above description are given. For example, inthe case of an oxide semiconductor film with an atomic ratio ofIn:Ga:Zn=1:1:1, the density of single-crystal InGaZnO₄ with arhombohedral crystal structure is 6.357 g/cm³. Thus, for example, in thecase of the oxide semiconductor film with an atomic ratio ofIn:Ga:Zn=1:1:1, the density of an a-like OS film is higher than or equalto 5.0 g/cm³ and lower than 5.9 g/cm³. In addition, for example, in thecase of the oxide semiconductor film with an atomic ratio ofIn:Ga:Zn=1:1:1, the density of an nc-OS film or a CAAC-OS film is higherthan or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that single crystals with the same composition do not exist in somecases. In such a case, by combining single crystals with differentcompositions at a given proportion, it is possible to calculate densitythat corresponds to the density of a single crystal with a desiredcomposition. The density of the single crystal with a desiredcomposition may be calculated using weighted average with respect to thecombination ratio of the single crystals with different compositions.Note that it is preferable to combine as few kinds of single crystals aspossible for density calculation.

Note that an oxide semiconductor film may be a stacked film includingtwo or more films of an amorphous oxide semiconductor film, an a-like OSfilm, a microcrystalline oxide semiconductor film, and a CAAC-OS film,for example.

Even when the oxide semiconductor film is a CAAC-OS film, a diffractionpattern similar to that of an nc-OS film or the like is partly observedin some cases. Therefore, whether or not a CAAC-OS film is favorable canbe determined by the proportion of a region where a diffraction patternof a CAAC-OS film is observed in a predetermined area (also referred toas proportion of CAAC). In the case of a high quality CAAC-OS film, forexample, the proportion of CAAC is higher than or equal to 50%,preferably higher than or equal to 80%, further preferably higher thanor equal to 90%, still further preferably higher than or equal to 95%.

<Off-State Current>

Unless otherwise specified, the off-state current in this specificationrefers to a drain current of a transistor in the off state (alsoreferred to as non-conduction state and cutoff state). Unless otherwisespecified, the off state of an n-channel transistor means that thevoltage between its gate and source (Vgs: gate-source voltage) is lowerthan the threshold voltage Vth, and the off state of a p-channeltransistor means that the gate-source voltage Vgs is higher than thethreshold voltage Vth. For example, the off-state current of ann-channel transistor sometimes refers to a drain current that flows whenthe gate-source voltage Vgs is lower than the threshold voltage Vth.

The off-state current of a transistor depends on Vgs in some cases. Forthis reason, when there is Vgs at which the off-state current of atransistor is lower than or equal to I, it may be said that theoff-state current of the transistor is lower than or equal to I. Theoff-state current of a transistor may refer to off-state current atgiven Vgs, off-state current at Vgs in a given range, or off-statecurrent at Vgs at which sufficiently low off-state current is obtained.

As an example, the assumption is made of an n-channel transistor wherethe threshold voltage Vth is 0.5 V and the drain current is 1×10⁻⁹ A atVgs of 0.5 V, 1×10⁻¹³ A at Vgs of 0.1 V, 1×10⁻¹⁹ A at Vgs of −0.5 V, and1×10⁻²² A at Vgs of −0.8 V. The drain current of the transistor is1×10⁻¹⁹ A or lower at Vgs of −0.5 V or at Vgs in the range of −0.8 V to−0.5 V; therefore, it can be said that the off-state current of thetransistor is 1×10⁻¹⁹ A or lower. Since there is Vgs at which the draincurrent of the transistor is 1×10⁻²² A or lower, it may be said that theoff-state current of the transistor is 1×10⁻²² A or lower.

In this specification, the off-state current of a transistor with achannel width W is sometimes represented by a current value in relationto the channel width W or by a current value per given channel width(e.g., 1 μm). In the latter case, the unit of off-state current may berepresented by current per length (e.g., A/μm).

The off-state current of a transistor depends on temperature in somecases. Unless otherwise specified, the off-state current in thisspecification may be an off-state current at room temperature, 60° C.,85° C., 95° C., or 125° C. Alternatively, the off-state current may bean off-state current at a temperature at which the reliability of asemiconductor device or the like including the transistor is ensured ora temperature at which the semiconductor device or the like is used(e.g., temperature in the range of 5° C. to 35° C.). When there is Vgsat which the off-state current of a transistor at room temperature, 60°C., 85° C., 95° C., 125° C., a temperature at which the reliability of asemiconductor device or the like including the transistor is ensured, ora temperature at which the semiconductor device or the like is used(e.g., temperature in the range of 5° C. to 35° C.) is lower than orequal to I, it may be said that the off-state current of the transistoris lower than or equal to I.

The off-state current of a transistor depends on voltage Vds between itsdrain and source in some cases. Unless otherwise specified, theoff-state current in this specification may be an off-state current atVds with an absolute value of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-statecurrent may be an off-state current at Vds at which the reliability of asemiconductor device or the like including the transistor is ensured orVds used in the semiconductor device or the like. When there is Vgs atwhich the off-state current of a transistor is lower than or equal to Iat given Vds, it may be said that the off-state current of thetransistor is lower than or equal to I. Here, given Vds is, for example,0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, 20V, Vds at which the reliability of a semiconductor device or the likeincluding the transistor is ensured, or Vds used in the semiconductordevice or the like.

In the above description of off-state current, a drain may be replacedwith a source. That is, the off-state current sometimes refers to acurrent that flows through a source of a transistor in the off state.

In this specification, the term “leakage current” sometimes expressesthe same meaning as off-state current.

In this specification, the off-state current sometimes refers to acurrent that flows between a source and a drain when a transistor isoff, for example

Although the variety of films such as the metal film, the semiconductorfilm, the inorganic insulating film which are disclosed in thisspecification and the like can be formed by a sputtering method or aplasma chemical vapor deposition (CVD) method, such films may be formedby another method, for example, a thermal CVD method. A metal organicchemical vapor deposition (MOCVD) method or an atomic layer deposition(ALD) method, for example, may be employed as a thermal CVD method.

A thermal CVD method has an advantage that no defect due to plasmadamage is generated since it does not utilize plasma for forming a film.

Deposition by a thermal CVD method may be performed in such a mannerthat a source gas and an oxidizer are supplied at a time to the chamber,in which the pressure is set to an atmospheric pressure or a reducedpressure, and react with each other in the vicinity of the substrate orover the substrate.

Deposition by an ALD method may be performed in such a manner thatsource gases for reaction are sequentially introduced into the chamber,in which the pressure is set to an atmospheric pressure or a reducedpressure, and then the sequence of the gas introduction is repeated. Forexample, two or more kinds of source gases are sequentially supplied tothe chamber by switching respective switching valves (also referred toas high-speed valves). For example, a first source gas is introduced, aninert gas (e.g., argon or nitrogen) or the like is introduced at thesame time as or after the introduction of the first gas so that thesource gases are not mixed, and then a second source gas is introduced.Note that in the case where the first source gas and the inert gas areintroduced at a time, the inert gas serves as a carrier gas, and theinert gas may also be introduced at the same time as the introduction ofthe second source gas. Alternatively, the first source gas may beexhausted by vacuum evacuation instead of the introduction of the inertgas, and then the second source gas may be introduced. The first sourcegas is adsorbed on the surface of the substrate to form a first layer;then the second source gas is introduced to react with the first layer;as a result, a second layer is stacked over the first layer, so that athin film is formed. The sequence of the gas introduction is repeatedplural times until a desired thickness is obtained, whereby a thin filmwith excellent step coverage can be formed. The thickness of the thinfilm can be adjusted by the number of repetition times of the sequenceof the gas introduction; therefore, an ALD method makes it possible toaccurately adjust a thickness and thus is suitable for manufacturing aminute field effect transistor (FET).

The variety of films such as the metal film, the semiconductor film, andthe inorganic insulating film which have been disclosed in theembodiment can be formed by a thermal CVD method such as a MOCVD methodor an ALD method. For example, for forming an In—Ga—Zn—O film,trimethylindium, trimethylgallium, and dimethylzinc are used. Thechemical formula of trimethylindium is In(CH₃)₃. The chemical formula oftrimethylindium is Ga(CH₃)₃. The chemical formula of dimethylzinc isZn(CH₃)₂. Without limitation to the above combination, triethylgallium(chemical formula: Ga(C₂H₅)₃) can be used instead of trimethylgallium,and diethylzinc (chemical formula: Zn(C₂H₅)₂) can be used instead ofdimethylzinc.

For example, in the case where a hafnium oxide film is formed with adeposition apparatus employing ALD, two kinds of gases, i.e., ozone (O₃)as an oxidizer and a source material gas which is obtained by vaporizingliquid containing a solvent and a hafnium precursor compound (hafniumalkoxide or hafnium amide such as tetrakis(dimethylamide)hafnium(TDMAH)) are used. The chemical formula oftetrakis(dimethylamide)hafnium is Hf[N(CH₃)₂]₄. Examples of anothermaterial liquid include tetrakis(ethylmethylamide)hafnium.

For example, in the case where an aluminum oxide film is formed by adeposition apparatus using an ALD method, two kinds of gases, e.g., H₂Oas an oxidizer and a source gas which is obtained by vaporizing liquidcontaining a solvent and an aluminum precursor compound (e.g.,trimethylaluminum (TMA)) are used. The chemical formula oftrimethylaluminum is Al(CH₃)₃. Examples of another material liquidinclude tris(dimethylamide)aluminum, triisobutylaluminum, and aluminumtris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, in the case where a silicon oxide film is formed by adeposition apparatus using an ALD method, hexachlorodisilane is adsorbedon a surface where a film is to be formed, chlorine contained in theadsorbate is removed, and radicals of an oxidizing gas (e.g., O₂ ordinitrogen monoxide) are supplied to react with the adsorbate.

For example, in the case where a tungsten film is formed using adeposition apparatus employing ALD, a WF₆ gas and a B₂H₆ gas aresequentially introduced a plurality of times to form an initial tungstenfilm, and then a WF₆ gas and an H₂ gas are alternately introduced, sothat a tungsten film is formed. Note that an SiH₄ gas may be usedinstead of a B₂H₆ gas.

For example, in the case where an oxide semiconductor film, e.g., anIn—Ga—Zn—O film is formed using a deposition apparatus employing ALD, anIn(CH₃)₃ gas and an O₃ gas are sequentially introduced a plurality oftimes to form an In—O layer, a Ga(CH₃)₃ gas and an O₃ gas are introducedto form a GaO layer, and then a Zn(CH₃)₂ gas and an O₃ gas areintroduced to form a ZnO layer. Note that the order of these layers isnot limited to this example. A mixed compound layer such as an In—Ga—Olayer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by using thesegases. Note that although an H₂O gas which is obtained by bubbling waterwith an inert gas such as Ar may be used instead of an O₃ gas, it ispreferable to use an O₃ gas, which does not contain H. Further, insteadof an In(CH₃)₃ gas, an In(C₂H₅)₃ gas may be used. Instead of a Ga(CH₃)₃gas, a Ga(C₂H₅)₃ gas may be used. Furthermore, a Zn(CH₃)₂ gas may beused.

This embodiment can be combined with any other embodiment asappropriate.

Embodiment 8

In this embodiment, examples of an electronic device including theimaging device of one embodiment of the present invention are described.

Examples of an electronic device including the imaging device of oneembodiment of the present invention are as follows: display devices suchas televisions and monitors, lighting devices, desktop personalcomputers and laptop personal computers, word processors, imagereproduction devices which reproduce still images and moving imagesstored in recording media such as digital versatile discs (DVDs),portable CD players, radios, tape recorders, headphone stereos, stereos,navigation systems, table clocks, wall clocks, cordless phone handsets,transceivers, mobile phones, car phones, portable game machines, tabletterminals, large game machines such as pinball machines, calculators,portable information terminals, electronic notebooks, e-book readers,electronic translators, audio input devices, video cameras, digitalstill cameras, electric shavers, high-frequency heating appliances suchas microwave ovens, electric rice cookers, electric washing machines,electric vacuum cleaners, water heaters, electric fans, hair dryers,air-conditioning systems such as air conditioners, humidifiers, anddehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers,electric refrigerators, electric freezers, electricrefrigerator-freezers, freezers for preserving DNA, flashlights,electric power tools such as chain saws, smoke detectors, medicalequipment such as dialyzers, facsimiles, printers, multifunctionprinters, automated teller machines (ATM), and vending machines.Further, industrial equipment such as guide lights, traffic lights, beltconveyors, elevators, escalators, industrial robots, power storagesystems, and power storage devices for leveling the amount of powersupply and smart grid can be given. In addition, moving objects and thelike driven by fuel engines and electric motors using power fromnon-aqueous secondary batteries are also included in the category ofelectronic devices. Examples of the moving objects included in thecategory of an electronic device are electric vehicles (EV), hybridelectric vehicles (HEV) which include both an internal-combustion engineand a motor, plug-in hybrid electric vehicles (PHEV), tracked vehiclesin which caterpillar tracks are substituted for wheels of thesevehicles, motorized bicycles including motor-assisted bicycles,motorcycles, electric wheelchairs, golf carts, boats, ships, submarines,helicopters, aircrafts, rockets, artificial satellites, space probes,planetary probes, and spacecrafts.

FIG. 22A illustrates a video camera, which includes a first housing1041, a second housing 1042, a display portion 1043, operation keys1044, a lens 1045, a joint 1046, and the like. The operation keys 1044and the lens 1045 are provided for the first housing 1041, and thedisplay portion 1043 is provided for the second housing 1042. The firsthousing 1041 and the second housing 1042 are connected to each otherwith the joint 1046, and an angle between the first housing 1041 and thesecond housing 1042 can be changed with the joint 1046. Images displayedon the display portion 1043 may be switched in accordance with the angleat the joint 1046 between the first housing 1041 and the second housing1042. The imaging device of one embodiment of the present invention canbe provided in a focus position of the lens 1045.

FIG. 22B illustrates a mobile phone which includes a display portion1052, a microphone 1057, a speaker 1054, a camera 1059, an input-outputterminal 1056, an operation button 1055, and the like in a housing 1051.For the camera 1059, the imaging device of one embodiment of the presentinvention can be used.

FIG. 22C illustrates a digital camera which includes a housing 1021, ashutter button 1022, a microphone 1023, a light-emitting portion 1027, alens 1025, and the like. The imaging device of one embodiment of thepresent invention can be provided in a focus position of the lens 1025.

FIG. 22D illustrates a portable game machine which includes a housing1001, a housing 1002, a display portion 1003, a display portion 1004, amicrophone 1005, a speaker 1006, an operation key 1007, a stylus 1008, acamera 1009, and the like. Although the portable game machineillustrated in FIG. 22D has the two display portions 1003 and 1004, thenumber of display portions included in the portable game machine is notlimited to this. The imaging device of one embodiment of the presentinvention can be used for the camera 1009.

FIG. 22E illustrates a wrist-watch-type information terminal whichincludes a housing 1031, a display portion 1032, a wristband 1033, acamera 1039, and the like. The display portion 1032 may be a touchpanel. The imaging device of one embodiment of the present invention canbe used for the camera 1039.

FIG. 22F illustrates a portable data terminal which includes a firsthousing 1011, a display portion 1012, a camera 1019, and the like. Atouch panel function of the display portion 1012 enables input andoutput of information. The imaging device of one embodiment of thepresent invention can be used for the camera 1019.

Needless to say, one embodiment of the present invention is not limitedto the above-described electronic devices as long as the imaging deviceof one embodiment of the present invention is included.

This embodiment can be combined with any other embodiment asappropriate.

This application is based on Japanese Patent Application serial no.2014-222882 filed with Japan Patent Office on Oct. 31, 2014, the entirecontents of which are hereby incorporated by reference.

What is claimed is:
 1. A semiconductor device comprising: a pixel portion comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first pixel, the second pixel, the third pixel, and the fourth pixel; a first wiring located outside the first pixel, the second pixel, the third pixel, and the fourth pixel; a second wiring electrically connected to the first pixel and the second pixel; and a third wiring electrically connected to the third pixel and the fourth pixel, wherein a first terminal of the first switch is electrically connected to the first wiring, wherein a second terminal of the first switch is electrically connected to the second wiring, wherein a first terminal of the second switch is electrically connected to the first wiring, and wherein a second terminal of the second switch is electrically connected to the third wiring.
 2. The semiconductor device according to claim 1, further comprising a fourth wiring configured to supply a reset potential to the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein a potential higher than the fourth wiring is supplied to the first wiring.
 3. An imaging device comprising: a photodetector portion including the semiconductor device according to claim 1; and a data processing portion capable of generating an image data in accordance with a signal from the photodetector portion.
 4. An electronic device comprising: the semiconductor device according to claim 1; and at least one of a lens, a display portion, an operation key, and a shutter button.
 5. A semiconductor device comprising: a pixel portion comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first pixel, the second pixel, the third pixel, and the fourth pixel; a first wiring located outside the first pixel, the second pixel, the third pixel, and the fourth pixel; a second wiring electrically connected to the first pixel and the second pixel; and a third wiring electrically connected to the third pixel and the fourth pixel, wherein a first terminal of the first switch is electrically connected to the first wiring, wherein a second terminal of the first switch is electrically connected to the second wiring, wherein a first terminal of the second switch is electrically connected to the first wiring, wherein a second terminal of the second switch is electrically connected to the third wiring, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are configured to be reset in a first step, wherein the first switch is configured to be turned on, a potential of the first wiring is configured to be supplied to the second wiring, and an electric signal is configured to be read from the first pixel and the second pixel in a second step after the first step, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are configured to be reset in a third step after the second step, and wherein the second switch is configured to be turned on, a potential of the first wiring is configured to be supplied to the third wiring, and an electric signal is configured to be read from the third pixel and the fourth pixel in a fourth step after the third step.
 6. The semiconductor device according to claim 5, further comprising a fourth wiring configured to supply a reset potential to the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein a potential higher than the fourth wiring is supplied to the first wiring.
 7. The semiconductor device according to claim 5, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel each include a photoelectric conversion element and a transistor, wherein the photoelectric conversion element is electrically connected to the transistor, and wherein a channel formation region of the transistor includes an oxide semiconductor.
 8. The semiconductor device according to claim 7, wherein the photoelectric conversion element includes a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and wherein the photoelectric conversion layer contains selenium.
 9. The semiconductor device according to claim 5, wherein the first switch is a first transistor, wherein the second switch is a second transistor, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel each include a photoelectric conversion element and a third transistor, wherein the photoelectric conversion element is electrically connected to the third transistor, wherein a channel formation region of each of the first transistor and the second transistor includes a single-crystal semiconductor, wherein a channel formation region of the third transistor includes an oxide semiconductor, and wherein the third transistor is stacked over the first transistor and the second transistor.
 10. The semiconductor device according to claim 9, wherein the photoelectric conversion element includes a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and wherein the photoelectric conversion layer contains selenium.
 11. An imaging device comprising: a photodetector portion including the semiconductor device according to claim 5; and a data processing portion capable of generating an image data in accordance with a signal from the photodetector portion.
 12. An electronic device comprising: the semiconductor device according to claim 5; and at least one of a lens, a display portion, an operation key, and a shutter button.
 13. A semiconductor device comprising: a pixel portion comprising a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first pixel, the second pixel, the third pixel, and the fourth pixel; a first wiring located outside the first pixel, the second pixel, the third pixel, and the fourth pixel; a second wiring electrically connected to the first pixel and the second pixel; and a third wiring electrically connected to the third pixel and the fourth pixel, wherein a first terminal of the first switch is electrically connected to the first wiring, wherein a second terminal of the first switch is electrically connected to the second wiring, wherein a first terminal of the second switch is electrically connected to the first wiring, wherein a second terminal of the second switch is electrically connected to the third wiring, and wherein the first pixel, the second pixel, the third pixel, and the fourth pixel each include a photoelectric conversion element.
 14. The semiconductor device according to claim 13, further comprising a fourth wiring configured to supply a reset potential to the first pixel, the second pixel, the third pixel, and the fourth pixel, wherein a potential higher than the fourth wiring is supplied to the first wiring.
 15. The semiconductor device according to claim 13, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel each include a transistor, wherein the photoelectric conversion element is electrically connected to the transistor, and wherein a channel formation region of the transistor includes an oxide semiconductor.
 16. The semiconductor device according to claim 13, wherein the first switch is a first transistor, wherein the second switch is a second transistor, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel each include a third transistor, wherein the photoelectric conversion element is electrically connected to the third transistor, wherein a channel formation region of each of the first transistor and the second transistor includes a single-crystal semiconductor, wherein a channel formation region of the third transistor includes an oxide semiconductor, and wherein the third transistor is stacked over the first transistor and the second transistor.
 17. The semiconductor device according to claim 13, wherein the photoelectric conversion element includes a first electrode, a second electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and wherein the photoelectric conversion layer contains selenium.
 18. An imaging device comprising: a photodetector portion including the semiconductor device according to claim 13; and a data processing portion capable of generating an image data in accordance with a signal from the photodetector portion.
 19. An electronic device comprising: the semiconductor device according to claim 13; and at least one of a lens, a display portion, an operation key, and a shutter button. 